Apple iPhone 8 PLUS (D21 MLB


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Sub Designs
04/14/2017
04/14/2017
WiFiANTFeeds
27
SYSTEM POWER: PMU (4/4)
SYSTEM POWER: B2B Battery
SYSTEM POWER: B2B Cyclone
AUDIO: Speaker Amp Bottom
AUDIO: CODEC (2/2)
sync
4
04/14/2017
04/14/2017
04/14/2017
04/14/2017
04/14/2017
66
16
LOWER ANTENNA
UPPER ANTENNA
SIM, DEBUG CONN
5
sync
SYSTEM POWER: PMU LDOs (3/4)
sync
68
17
11/28/2016
BB: CONTROL & HS PERIPHERALS [6]
62
I/O: USB PD
I/O: Hydra
I/O: B2B DOCK
07/18/2016
10
15
SOC: Power (1/3)
SOC: Power (2/3)
SYSTEM POWER: PMU Bucks (1/4)
SYSTEM POWER: PMU Bucks (2/4)
sync
sync
04/14/2017
sync
sync
04/14/2017
75
04/14/2017
SOC: MIPI + ISP
sync
04/14/2017
04/14/2017
04/14/2017
04/14/2017
04/14/2017
18
TEST POINTS
SYNC
CONTENTS
CSA
PAGE
DATE
SYNC
CONTENTS
CSA
PAGE
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
SUB-DESIGN NAME
VERSION
HARD/
REV
DESCRIPTION OF REVISION
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
APPD
1
1
2
4
5
6
7
B
D
6
5
4
3
C
A
A
D
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
PART NUMBER
QTY
DESCRIPTION
PART#
CRITICAL
QTY
DESCRIPTION
PART#
CRITICAL
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
QTY
DESCRIPTION
PART#
CRITICAL
QTY
DESCRIPTION
PART#
CRITICAL
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
Load Switch
Isolator Switch
NAND BOM Options
Global Ferrites Alternates
BUCK1 Slave
BUCK5/7
BUCK8/9/10
BUCK1 Master
Boost Alt
BUCK1 Slave
BUCK0 Slave
BUCK0/2/4/11 Master
PMID1 Zener Diode
ZRB Caps
Global R/C Alternates
10.0.0
3 OF 80
051-02159
MUR,CAP,ZRB,2.2UF,25V,0402
1
335S00287
ALL
138S00151
ALL
138S00150
132S0296
1
335S00240
371S00121
DZ3300
ALL
152S00621
ALL
152S00713
ALL
152S00622
CAP,CER,X5R,0.1UF,20%,6.3V,01005
353S00576
U5890
STMICRO LDO
353S00999
U6100
U6100
197S00120
197S00118
ALL
152S00711
ALL
ALL
152S00654
152S00656
ALL
152S00651
ALL
152S00716
152S00626
152S00717
ALL
152S00631
152S00632
ALL
ALL
152S00640
152S00641
152S00721
155S00067
ALL
155S00194
ALL
ALL
152S00557
155S0876
155S00340
155S0660
155S00339
155S0661
IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016
152S00622
IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012
155S0610
138S00164
138S00138
138S00165
138S00163
138S00049
138S0831
138S00140
ALL
138S00166
ALL
138S00140
ALL
138S00048
138S00003
BOM_TABLE_ALTS
132S0639
138S00145
ALL
138S00138
ALL
ALL
132S0400
138S0739
U2600
335S00287
U2600
335S00287
T,BiCS3,ULTIMATE
S,BiCS3,ULTIMATE
U2600
335S00288
335S00240
U2600
SS,3Dv4,EXTREME
U2600
335S00247
335S00240
U2600
335S00228
335S00240
SS,3Dv4,ULTIMATE
335S00287
335S00286
311S00114
SPDT,TI
311S00126
197S0612
155S00168
CAP,X5R,4.7UF,6.3V,0.65MM,0402
132S0400
138S00024
138S00139
138S00138
197S00120
CAP,CER,NP0/C0G,27PF,5%,16V,01005
131S00053
RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201
107S0257
CAP,CER,X5R,0.1UF,10%,16V,0201
132S0249
CAP,CER,NP0/C0G,220PF,2%,50V,0201
132S00008
CAP,CER,NP0/C0G,100PF,5%,16V,01005
197S0446
CAP,CER,X5R,1UF,20%,6.3V,0201
138S00128
0201,[email protected]
138S00141
138S0739
138S0706
138S0945
138S0739
ALL
118S0717
1
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
QTY
DESCRIPTION
PART#
CRITICAL
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
PART NUMBER
COMMENT
COMMENT
COMMENT
COMMENT
COMMENT
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
COMMENT
COMMENT
COMMENT
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
COMMENT
COMMENT
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
COMMENT
QTY
DESCRIPTION
PART#
CRITICAL
COMMENT
O
O
10.0.0
4 OF 80
051-02159
ZT0408
STDOFF-2.57OD1.43ID-0.899H-SM
16V
NP0-C0G
5%
16V
01005
16V
01005
NP0-C0G
5%
SM
STDOFF-2.9OD0.81H-SM1
C0G-CERM
5%
5%
01005
10V
C0G-CERM
10V
01005
5%
01005
NP0-C0G-CERM
25V
5%
NP0-C0G-CERM
5%
01005
01005
16V
CERM
2%
16V
CERM
2%
4PF
16V
NP0-C0G
16V
01005
NP0-C0G
+/-0.1PF
16V
CERM
01005
16V
NP0-C0G
+/-0.1PF
220PF
01005
5%
C0G-CERM
NP0-C0G-CERM
5%
01005
C0G-CERM
5%
01005
10V
2%
16V
NP0-C0G
01005
16V
+/-0.1PF
C0G-CERM
5%
10V
01005
5%
ROOM=ASSEMBLY
FID
0P5SQ-SMP3SQ-NSP
ROOM=ASSEMBLY
ROOM=ASSEMBLY
SYNC_DATE=04/14/2017
CHASSIS_GND_BS401
CHASSIS_GND_BS401
CHASSIS_GND_BS402
CHASSIS_GND_BS402
2
1
1
4
34
4
34
4
4
4
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
MOJAVE
RF Debug
PMU Debug
LCM BACKLIGHT SINK2
ANALOG MUX B OUTPUT
VDD_MAIN
LVCC TP
POWER GROUND
VBATT
VBUS1
VBUS2
CALLISTO
IN THE FACTORY FIXTURE.
TP IS TO HELP WITH USB SI
FOR DIAGS
FORCE DFU
E75
POWER
NAND Debug
BB UAT Debug
LCM BACKLIGHT SINK3
Sensor SPI
#29162687:CODEC BCLK
#29794618:CCG2
BACKLIGHT Debug
5 OF 80
051-02159
1
1
1
1
AP_VDD_GPU_SENSE
PMU_AMUX_AY
WLAN_TO_AP_TIME_SYNC
PP_CPU_PCORE
AP_CPU_PCORE_SENSE
TP_SOC_SENSE
TP_VSS_CPU_SENSE
TP_VSS_SENSE
DWI_PMGR_TO_BACKLIGHT_CLK
DWI_PMGR_TO_BACKLIGHT_DATA
UAT_TUNER_RFFE_DATA
AP_TO_NFC_FW_DWLD_REQ
SPI_AOP_TO_IMU_SCLK
TP_VDD_DCS_SENSE
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
90_PCIE_AP_TO_NAND_REFCLK_P
HYDRA_TO_TIGRIS_VBUS1_VALID_L
90_PCIE_AP_TO_NAND_REFCLK_N
SPMI_PMU_BI_PMGR_SDATA
UAT_TUNER_RFFE_CLK
PP1V8_S2
SWD_AOP_TO_MANY_SWCLK
NAND_ANI1_VREF
PP_CPU_PCORE_LVCC
AP_GPU_GND_SENSE
PP_DISPLAY_BL34_ANODE_CONN
PP_DISPLAY_BL34_CAT2_CONN
PP_DISPLAY_BL12_CAT2_CONN
PP_DISPLAY_BL12_CAT1_CONN
PP_DISPLAY_BL34_CAT1_CONN
PP_DISPLAY_BL12_ANODE_CONN
PP16V0_MESA_CONN
PMU_AMUX_BY
MESA_TO_BOOST_EN_CONN
ROOM=TEST
TP-P55
ROOM=TEST
TP-P55
ROOM=TEST
11
17
13
17
13
16
16
48
47
46
44
33
20
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
50
50
7
9
12
6
14
21
14
15
13
17
8
17
8
27
13
27
13
27
13
47
24
ROOM=TEST
TP-P55
ROOM=TEST
TP-P55
ROOM=TEST
ROOM=TEST
TP-P55
ROOM=TEST
TP-P55
ROOM=TEST
42
42
42
42
42
42
43
21
43
48
48
48
48
47
48
47
48
47
48
47
47
21
12
12
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
26
25
26
25
24
23
48
24
25
24
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
0010 DVT
Note: Future board revs TBD
1000 EVT
xxxx SPARE
xxxx SPARES
00100 D21 MLB
01010 D201 MLB
0=EUREKA, 1=KAROO
1011 PROTO2 (HALOGEN DOE)
001 SPI0 TEST MODE
FLOAT=LOW, PULLUP=HIGH
111 FAST SPI0 TEST
No connect
110 SLOW SPI0 TEST
1001 PROTO2v5
0000 PVT
01101 D211 DEV
0=MLB, 1=DEV
01=D20x, 10=D21x
00011 D20 DEV
100 n/a
01100 D211 MLB
000 SPI0
BOARD ID
BOOT CONFIG
FLOAT=LOW, PULLUP=HIGH
xxxx SPARES
�SELECTED --
1100 PROTO2
1101 SPARE
1110 PROTO1
00101 D21 DEV
01011 D201 DEV
10.0.0
6 OF 80
051-02159
1
1
1
1
1
1
1
1
1
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
BOARD_ID0
BOARD_ID1
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
BOARD_REV0
BOARD_ID3
BOARD_REV3
BOARD_REV1
BOARD_ID2
BOARD_ID4
BOARD_REV2
PP1V8_IO
SYNC_MASTER=sync
5%
01005
5%
1/32W
MF
1/32W
5%
01005
MF
01005
1/32W
MF
ROOM=SOC
MF
5%
1/32W
5%
1/32W
01005
MF
1/32W
1%
MF
1/32W
11
17
11
12
5
12
17
11
5
12
11
12
12
12
12
12
42
40
33
31
30
29
28
18
17
15
11
9
8
7
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
0.765V - 0.84V @ 5mA MAX
VDD18_XTAL:1.62-1.98V @ 2mA MAX
7 OF 81
051-02159
10.0.0
GND
GND
3
1
2
1
BA28
AW5
AN14
AU28
AT7
AU8
AW6
AY6
BA6
AY4
BA4
V2
W4
AF34
AG38
A30
AV6
AT10
AT9
AT12
AT13
AT8
W5
AD3
AD2
B31
AW21
AT22
AU7
AV5
AT34
AT27
1
1
1
1
1
1
1
AP_TO_PMU_SOCHOT_L
AP_USB_REXT
PP1V8_XTAL
AP_TO_NAND_FW_STRAP
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GND
VDD18_XTAL
VDD18_USB
VDD33_USB
VDD_FIXED_USB
XI0
CPU_TRIGGER0
USB_REXT
DROOP
SOCHOT1
WDOG
CPU_TRIGGER1
GPU_TRIGGER0
GPU_TRIGGER1
USB_ID
USB_VBUS
USB_DP
USB_DM
ANALOGMUX_OUT
SSD_BFH
TESTMODE
PCIE LINK 3
PCIE LINK 2
30
29
28
18
17
15
11
9
8
7
6
50
8
20
15
14
10
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
18
15
14
10
9
7
17
8
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
LINK1
LINK2
LINK3
LINK0
PCIE_REF_CLK3_N
PCIE_REF_CLK3_P
PCIE_CLKREQ2*
PCIE_RX3_N
PCIE_REF_CLK2_P
PCIE_REF_CLK2_N
PCIE_PERST3*
PCIE_TX3_P
PCIE_TX3_N
PCIE_RX3_P
PCIE_TX2_N
PCIE_TX2_P
PCIE_PERST2*
PCIE_RX2_N
PCIE_RX2_P
PCIE_REXT
PCIE_CLKREQ0*
PCIE_REF_CLK0_P
PCIE_REF_CLK0_N
PCIE_TX0_N
PCIE_TX0_P
PCIE_RX0_N
PCIE_RX0_P
PCIE_REF_CLK1_P
PCIE_CLKREQ1*
PCIE_PERST0*
PCIE_REF_CLK1_N
PCIE_RX1_N
PCIE_RX1_P
PCIE_EXT_REF_CLK_P
PCIE_EXT_REF_CLK_N
PCIE_PERST1*
PCIE_TX1_P
VDD_FIXED_PCIE_REFBUF
VDD_FIXED_PCIE_ANA
VDD_FIXED_PCIE_ANA
VDD18_PCIE
VDD18_PCIE
VDD12_PCIE_REFBUF
VDD12_PCIE_REFBUF
�SOC D3 - DISPLAY D1 (N & P SWAP)
ISP I2C0
DISPLAY MIPI LANE SWAPS
Pin assignment optimized for D21/D211 MLB
10.0.0
12 OF 80
051-02159
1
1
G12
F13
F11
AA35
AC37
R37
T37
U35
U36
R38
U37
V34
V36
U38
D11
A6
A7
A10
A8
B6
B7
A9
B10
B8
D13
B15
B17
A16
A15
A17
B16
D12
B14
B12
A13
A14
B13
AB38
AA37
Y38
Y34
Y36
W36
V38
W35
AB6
AB4
AA3
Y4
AA5
AA4
1
1
1
I2C2_ISP_SDA
PP1V8_IO
PP1V8_IO
PP1V8_IO
90_MIPI_FCAM_TO_AP_CLK_N
90_MIPI_FCAM_TO_AP_CLK_P
90_MIPI_FCAM_TO_AP_DATA1_N
90_MIPI_FCAM_TO_AP_DATA0_N
90_MIPI_FCAM_TO_AP_DATA0_P
90_MIPI_AP_TO_DISPLAY_DATA0_P
90_MIPI_AP_TO_DISPLAY_DATA0_N
90_MIPI_AP_TO_DISPLAY_DATA3_P
90_MIPI_AP_TO_DISPLAY_DATA3_N
90_MIPI_AP_TO_DISPLAY_DATA2_P
90_MIPI_AP_TO_DISPLAY_DATA1_N
90_MIPI_AP_TO_DISPLAY_DATA2_N
90_MIPI_AP_TO_DISPLAY_DATA1_P
90_MIPI_AP_TO_DISPLAY_CLK_P
MIPID_REXT
MIPI0C_REXT
PP1V8_IO
PP0V8_SOC_FIXED_S1
I2C3_ISP_SDA
I2C3_ISP_SCL
I2C0_ISP_SCL
I2C1_ISP_SDA
I2C0_ISP_SDA
I2C1_ISP_SCL
I2C1_ISP_SDA
PP1V8_IO
I2C0_ISP_SCL
I2C0_ISP_SDA
I2C1_ISP_SCL
I2C2_ISP_SCL
I2C2_ISP_SDA
AP_TO_WIDE_CLK
AP_TO_TELE_CLK
AP_TO_FCAM_CLK
AP_TO_FCAM_CLK_R
AP_TO_MUON_BL_STROBE_EN
ISP_TO_FCAM_SHUTDOWN_L
ISP_TO_TELE_SHUTDOWN_L
AP_TO_TELE_CLK_R
AP_TO_WIDE_CLK_R
I2C3_ISP_SCL
I2C3_ISP_SDA
90_MIPI_FCAM_TO_AP_DATA1_P
SYNC_MASTER=sync
31
MF
1/32W
1/32W
MF
01005
MF
1/32W
01005
9
31
9
30
01005
1/32W
1/32W
MF
5%
MF
1/32W
5%
01005
1/32W
01005
MF
1/32W
42
42
42
41
5
33
30
29
9
32
29
9
33
9
33
9
30
9
30
9
42
42
42
42
42
42
33
33
33
33
1/32W
5%
1/32W
MF
01005
MF
1/32W
MF
20%
01005
20%
X5R-CERM
01005
6.3V
0201
6.3V
X5R-CERM
20%
9
33
9
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
18
15
14
10
8
7
29
9
32
9
31
9
31
9
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
30
9
30
9
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
ISP_I2C1_SDA
ISP_I2C2_SDA
ISP_I2C2_SCL
ISP_I2C0_SDA
ISP_I2C1_SCL
ISP_I2C0_SCL
ISP_I2C3_SDA
SENSOR_INT
SENSOR0_CLK
SENSOR1_CLK
SENSOR0_RST
SENSOR0_XSHUTDOWN
SENSOR1_ISTRB
SENSOR0_ISTRB
MIPI0C_DNCLK
MIPI0C_REXT
MIPI0C_DPCLK
MIPI0C_DNDATA1
MIPI0C_DPDATA1
MIPI0C_DNDATA0
MIPI0C_DPDATA0
MIPI1C_REXT
MIPI1C_DNDATA0
MIPI1C_DPDATA1
MIPI1C_DNCLK
MIPI1C_DPCLK
MIPI1C_DPDATA0
MIPID_DPDATA0
MIPID_DNDATA0
MIPID_DPDATA1
MIPID_DNDATA1
MIPID_DPDATA2
MIPID_DPDATA3
MIPID_DNDATA2
MIPID_DNDATA3
DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1
DISP_TOUCH_EB
MIPID_DNCLK
MIPID_REXT
MIPID_DPCLK
DISP_I2C_SDA
DISP_POL
DISP_I2C_SCL
VDD_FIXED_MIPI
�SOC D3 - TELE D2
VDD_FIXED_LPDP_RX:0.765V - 0.84V @ 47mA MAX
�SOC D5 - TELE D1
�SOC D4 - TELE D0
GND
13 OF 80
051-02159
1
P9
G18
G16
T9
M9
F16
F17
B19
A20
B20
A21
B21
A24
B24
A25
B25
A26
B26
B23
A23
D18
A22
B22
D15
D16
J4
J5
K3
K4
L4
L5
M3
M4
H6
H3
G4
G5
Y6
Y2
1
1
PP1V2_SOC
90_LPDP_WIDE_TO_AP_D0_P
90_LPDP_WIDE_TO_AP_D2_N
90_LPDP_WIDE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D0_N
90_LPDP_WIDE_TO_AP_D1_P
90_LPDP_WIDE_TO_AP_D1_N
LPDP_TELE_BI_AP_AUX
AP_LPDPRX_RCAL_NEG
PP0V8_SOC_FIXED_S1
90_LPDP_TELE_TO_AP_D0_P
90_LPDP_TELE_TO_AP_D2_N
90_LPDP_TELE_TO_AP_D1_N
LPDP_WIDE_BI_AP_AUX
90_LPDP_TELE_TO_AP_D1_P
90_LPDP_WIDE_TO_AP_D0_N
SYNC_MASTER=sync
MF
1%
NP0-C0G-CERM
5%
16V
0201
20%
X5R-CERM
01005
X5R-CERM
20%
16V
5%
31
31
31
31
31
31
0201
20%
X5R-CERM
X5R-CERM
20%
30
30
30
30
30
30
18
15
14
10
9
8
7
20
15
14
8
18
15
14
10
9
8
7
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VDD_FIXED_LPDP_TX
LPDP_TX0P
LPDP_TX1P
LPDP_TX1N
LPDP_TX2P
LPDP_TX2N
LPDP_TX3P
LPDP_TX3N
LPDP_CAL_DRV_OUT
LPDP_AUX_P
LPDP_AUX_N
LPDP_CAL_VSS_EXT
EDP_HPD
DP_WAKEUP
LPDPRX_RX_D0_P
LPDPRX_RX_D1_N
LPDPRX_RX_D1_P
LPDPRX_RX_D0_N
LPDPRX_RX_D2_N
LPDPRX_RX_D3_N
LPDPRX_RX_D3_P
LPDPRX_RX_D2_P
LPDPRX_RX_D4_P
LPDPRX_RX_D5_N
LPDPRX_RX_D5_P
LPDPRX_RX_D4_N
LPDPRX_AUX_D0_P
LPDPRX_BYP_CLK_P
LPDPRX_BYP_CLK_N
LPDPRX_AUX_D2_P
LPDPRX_AUX_D1_P
LPDPRX_AUX_D4_P
LPDPRX_AUX_D3_P
LPDPRX_AUX_D5_P
LPDPRX_RCAL_P
LPDPRX_RCAL_N
LPDPRX_EXT_C
VDD12_PLL_LPDP
VDD12_LPDP_RX
VDD12_LPDP_TX
AP I2C1
SMC I2C0
SMC I2C1
5
17
6
6
43
43
43
1/32W
MF
1/32W
01005
MF
1/32W
01005
0%
1/32W
25
24
23
22
11
48
42
41
11
48
42
41
11
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
46
25
24
23
22
11
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
47
11
47
11
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
48
34
11
48
34
11
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
45
41
21
11
45
41
21
11
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
38
33
11
38
33
11
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
SPMI_SCLK
I2C0_SDA
I2C0_SCL
I2C1_SCL
I2C1_SDA
I2C3_SCL
I2C3_SDA
SMC_I2CM0_SCL
SEP_SPI0_MISO
SMC_I2CM1_SDA
SMC_UART0_TXD
SEP_SPI0_SCLK
SEP_SPI0_MOSI
SEP_I2C_SCL
SEP_I2C_SDA
I2C2_SCL
SMC_UART0_RXD
SMC_I2CM0_SDA
SMC_I2CM1_SCL
DWI_CLK
NAND_SYS_CLK
DWI_DO
CLK24M_OUT
I2S0_BCLK
I2S0_LRCK
I2S0_DOUT
I2S1_LRCK
I2S1_BCLK
I2S1_MCK
I2S0_DIN
I2S0_MCK
I2S2_MCK
I2S2_BCLK
I2S2_DIN
I2S1_DIN
I2S1_DOUT
I2S2_LRCK
I2S2_DOUT
SPI0_MISO
I2S3_MCK
I2S3_DOUT
I2S3_DIN
I2S3_BCLK
I2S3_LRCK
SPI0_SSIN
SPI1_SCLK
SPI1_SSIN
SPI1_MOSI
SPI1_MISO
SPI0_MOSI
SPI0_SCLK
SPI3_MISO
SPI3_MOSI
SPI2_SSIN
SPI2_SCLK
SPI3_SSIN
SOUTHWEST
NORTHEAST
EAST
10.0.0
15 OF 80
051-02159
R5
AF4
AF5
N35
N36
D31
C32
B30
C28
M37
P36
AF2
AF3
A28
C30
AC4
AB2
AK5
AK4
AJ6
AJ3
V3
V4
U2
T2
T5
R2
R3
P4
A32
D29
D32
C34
L35
K34
L37
N37
P38
R36
T35
AL4
BOARD_REV1
PMU_TO_AP_BUTTON_POWER_KEY_L
PMU_TO_AP_BUTTON_VOL_DOWN_L
BOARD_REV0
BOARD_REV2
UART_ACCESSORY_TO_AP_RXD
SPKRAMP_TOP_TO_AP_INT_L
UART_AP_TO_BT_RTS_L
UART_BT_TO_AP_RXD
UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_RTS_L
UART_AP_TO_NFC_TXD
UART_AP_TO_NFC_RTS_L
UART_GNSS_TO_AP_RXD
UART_AP_TO_GNSS_RTS_L
UART_AP_TO_GNSS_TXD
UART_GNSS_TO_AP_CTS_L
AP_TO_BB_IPC_GPIO1
AP_TO_NFC_FW_DWLD_REQ
AP_TO_GNSS_WAKE
PMU_TO_AP_PRE_UVLO_L
WLAN_TO_AP_TIME_SYNC
SYNC_DATE=04/14/2017
21
7
50
50
50
50
42
50
50
50
5
50
5
42
5
47
47
50
50
50
50
50
50
50
50
50
50
50
50
47
47
21
21
6
6
6
42
6
6
47
21
5
50
6
5
38
29
38
50
50
50
29
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
UART7_TXD
UART4_TXD
UART4_CTS*
UART3_CTS*
UART2_RTS*
UART1_RTS*
UART1_CTS*
UART0_TXD
UART0_RXD
UART1_TXD
UART2_CTS*
UART1_RXD
TMR32_PWM0
TMR32_PWM1
UART2_RXD
UART2_TXD
UART3_RXD
UART3_TXD
UART4_RTS*
UART4_RXD
UART3_RTS*
UART6_RXD
UART6_TXD
GPIO_0
GPIO_3
GPIO_4
GPIO_14
GPIO_12
GPIO_13
GPIO_11
GPIO_15
GPIO_20
GPIO_19
GPIO_16
GPIO_17
GPIO_23
GPIO_24
GPIO_22
GPIO_21
GPIO_26
GPIO_27
GPIO_31
GPIO_32
GPIO_37
GPIO_36
REQUEST_DFU2
REQUEST_DFU1
10.0.0
16 OF 80
051-02159
1
1
1
1
AP17
BA18
AY19
BA17
AT15
AU11
AW8
BA8
AT14
AT21
AY17
AV20
AV8
AU10
AW7
AW17
AW18
AU19
BA15
BA13
AT19
BA14
AW9
AV10
AV9
BA9
AY14
AW14
AT18
BA10
BA11
AY13
AU17
AW13
AV14
AW12
AV13
AT17
AV16
AU16
AY11
AT16
AW11
AU13
AU14
AT11
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
RT_CLK32768
AOP_SWD_TCK_OUT
AOP_SWD_TMS0
AOP_SWD_TMS1
AOP_PDM_DATA1
SWD_TMS2
DOCK_ATTENTION
AOP_PDM_DATA0
SWD_TMS3
AOP_I2CM0_SCL
AOP_I2CM1_SDA
AOP_I2CM1_SCL
AOP_I2CM0_SDA
DOCK_CONNECT
AOP_FUNC_0
0.7V @ 75mA MAX
0.575V @ 1.4A MAX
0.8V @ 2.8A MAX
1.06V @ 1.1A MAX
0.80V @ 0.63A MAX
0.735V @ 0.6A MAX
0.675V @ 0.19A MAX
0.575V @ 2.7A MAX
1.06V @ 11.0A MAX
0.8V @ 6A MAX
0.8V @ 10.6A MAX
0.575V @ 3.4A MAX
1.06V @ 18.3A MAX
0.765V @ 4.9A MAX
0.635V @ 2.6A MAX
1.2V @ 7mA MAX (GPU)
1.2V @ 20mA MAX (SOC)
1.2V @ 7mA MAX (CPU)
0.8V @ 6mA MAX
0.8V @ 6+10=16mA MAX
10.0.0
17 OF 80
051-02159
1
1
3
2
1
3
2
1
1
3
2
1
3
2
1
Y27
Y21
W22
W18
U18
U16
R24
R22
P19
P15
M13
L19
F22
AN24
AM25
AL30
AL18
AL16
AK27
AJ28
AJ24
AJ22
AH27
AG28
AF27
AE28
AD29
AD9
AC30
AB27
AA24
AA22
AA9
AM21
AM19
AM17
M29
G30
K23
H25
H13
N26
N23
N28
L28
L22
J22
J18
J28
G26
L20
K21
W14
Y15
Y13
V15
V13
U14
AF14
AE20
AC14
AC9
AB18
AH21
AH20
AH14
AH12
AG15
AG9
AF20
AE14
AD15
AB19
AB17
AB15
M20
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
3
2
1
1
1
3
2
1
3
2
1
3
1
3
2
1
TP_SOC_SENSE
BUCK0_FB
BUCK11_FB
PP1V2_SOC
AP_VDD_GPU_SENSE
AP_CPU_PCORE_SENSE
PP_GPU_SRAM
PP_CPU_SRAM
PP0V7_VDD_LOW_S2
PP0V8_SOC_FIXED_S1
PP0V8_SOC_FIXED_S1
PP_CPU_ECORE
BUCK1_FB
PP_SOC_S1
PP_GPU
PP_CPU_PCORE
SYNC_MASTER=sync
21
5
21
5
0201
6.3V
X5R-CERM
6.3V
X5R-CERM
20%
6.3V
4V
0201
X5R
4V
20%
4V
19
4V
0201
4V
0201
X5R
4V
4V
20%
0201
CER-X5R
18
5
18
X5R
4V
4V
20%
X5R
4V
X5R
4V
X5R
4V
X5R
4V
X5R
4V
X5R
4V
20%
X5R
4V
0402-D2X-1
0402-D2X-1
20%
X5R
4V
X5R
4V
X5R
4V
20%
X5R
4V
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VDD_SOC
VDD_ECPU
VDD_FIXED_PLL_GPU
VDD_FIXED_PLL_SOC
VDD12_PLL_CPU
VDD12_PLL_GPU
VDD_FIXED_CPU
VDD_CPU
VDD_LOW
VDD_CPU_SRAM
VDD_CPU_SENSE
VDD_GPU_SRAM
VDD_GPU_SENSE
1.2V @ 16mA MAX
1.06V - 1.17V @ (inc in VDD2)
1.06V - 1.17V @ 2.2A MAX
0.6V @ 620mA MAX
0.875V @ 0.8A MAX
0.730V @ 0.51A MAX
1.8V @ 5.3mA MAX (CPU)
1.8V @ 1.1mA MAX (GPU)
1.8V @ 1mA MAX
1.8V @ 1mA MAX
1.8V @ 200mA MAX
Place one cap per SoC corner
Place one cap per SoC corner
0.8V @ 0.9A MAX
DDR IMPEDANCE CONTROL
10.0.0
18 OF 80
051-02159
1
1
1
AF9
D23
F21
Y31
V31
AB31
AP25
AP23
J31
G21
Y16
AJ9
AF21
T12
AN19
1
T39
P39
P31
F39
D39
C4
V1
T1
K9
H1
F9
D1
AV39
AT39
AP39
AF39
AD39
AV1
AT1
AP9
AH1
AF1
AD1
T29
D9
AK29
AJ11
G34
E6
AN34
AR6
R30
K30
A4
L10
F10
AK30
AE30
AP10
AJ10
W1
J1
H39
AW2
AV37
AV2
AP1
Y37
Y3
AW37
AW3
AB37
AB3
N38
H34
H35
G35
E4
E5
E3
AM34
AN35
AM35
AJ2
AP6
AP5
AR5
D8
Y29
W26
W20
U26
T31
R26
P29
N20
M17
F23
AP24
AM23
AM11
AL26
AL20
AK23
AJ26
AJ14
AH29
AH23
AG26
AF29
AE26
AD31
AB29
AB9
AA26
BA19
AY20
1
1
3
2
1
LPADC_GND
PP1V2_LPADC
PP0V8_SOC_FIXED_S1
PP0V6_VDDQL_S1
PP1V8_IO
PP0V6_VDDQL_S1
AOP_TO_DDR_SLEEP1_READY
DDR3_RREF
DDR2_RREF
DDR3_ZQ
DDR0_ZQ
PP1V8_S2
PP1V2_SOC
PP1V1_S2
TP_VDD_DCS_SENSE
SYSTEM_ALIVE
PP1V1_S2
PP_DCS_S1
PP1V8_IO
PP1V8_LPOSC_S2
PP1V8_S2
PP1V8_IO
PP0V8_SOC_FIXED_S1
SYNC_MASTER=sync
5
24
21
17
6.3V
X5R
1/32W
MF
01005
6.3V
01005
X5R-CERM
NP0-C0G-CERM
01005
25V
5%
4V
20%
CER-X5R
CER-X5R
4V
20%
0201
20%
4V
20%
4V
20%
4V
0201
4V
20%
6.3V
20%
0201
20%
0201
0201
0201
20%
MF
1/32W
MF
1/32W
ROOM=SOC
CER-X5R
0201
CER-X5R
20%
CER-X5R
4V
20%
CER-X5R
20%
CER-X5R
4V
20%
0201
CER-X5R
4V
20%
0201
0201
20%
0201
0201
4V
20%
MF
1/32W
MF
1/32W
MF
1/32W
MF
1/32W
ROOM=SOC
X5R
0402-D2X-1
20
18
15
14
10
9
8
7
19
15
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
19
15
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
20
14
10
8
20
18
15
20
18
15
18
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
18
15
14
10
9
8
7
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VDD18_TSADC_CPU1
VDD18_LPOSC
VDD18_FMON
VDD18_EFUSE2
VDD18_EFUSE1
VDD18_TSADC_SOC2
VDD18_TSADC_SOC0
VDD18_TSADC_SOC1
VDD18_TSADC_GPU0
VDD18_TSADC_CPU3
VDD18_TSADC_CPU2
VDDIO18_GRP1
VDDIO18_GRP2
VDDIO18_GRP3
VDDIO18_GRP4
VDD_FIXED_PLL_DDR2
LPADC_REF_M
LPADC_REF_P
VDD_FIXED
10.0.0
19 OF 80
051-02159
AG21
Y39
Y35
Y30
Y28
W39
W38
W19
W17
V30
V28
V14
V6
U19
U17
U15
U9
T38
T34
T30
T10
T6
R39
R34
R19
R17
R6
P37
P28
P26
P5
P3
N34
N27
N9
M39
M38
M36
M6
M19
M10
L39
L3
L2
K16
K12
J36
J35
J17
J11
H24
H22
G38
G37
G6
G3
G1
F38
F36
F35
F6
F3
F2
F18
E39
E34
E2
E1
D37
D24
D22
D7
D14
D10
C39
C25
C24
C15
C14
C9
C5
C1
BA39
BA31
BA29
B39
B38
B1
AY39
AY25
AY23
AY5
AY3
AW24
AW4
AV24
AV4
AU31
AU9
AU27
AU24
AU21
AU2
AT38
AT32
AT31
AT5
AR39
AR37
AR4
AR3
AP38
AP12
AP4
AP3
AN38
AN23
AN21
AN6
AM39
AM18
AM16
AM6
AL39
AL35
AL34
AL21
AL19
AK35
AK34
AK12
AK10
AJ23
AJ21
AH28
AH26
AH5
AH3
AG6
AG1
AF6
AE39
AE29
AE27
AE25
AE9
AD37
AD24
AD22
AD6
AC35
AC27
AC25
AC6
AB39
AB30
AB28
AB5
AA39
AA23
AA21
AA6
A39
A11
A5
A3
TP_VSS_CPU_SENSE
TP_DDR_VSS_SENSE
SYNC_MASTER=sync
5
5
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VSS_SENSE
VSS
VSS
VSS
VSS
932mA MAX
1300mA MAX (1us peak power)
26 OF 80
051-02159
K3
G2
U10
U8
U2
T13
T9
T7
R10
P13
P7
P1
N10
N4
M13
M7
M5
L10
K13
K7
K5
K1
J10
H13
H9
F13
F11
F9
F7
D13
D1
C12
C2
B13
B1
A12
A8
F3
P9
T5
K9
J2
R4
R8
R6
R2
L12
E12
D3
L4
R12
T11
M11
N12
K11
J12
P5
M9
N6
E6
D7
E8
B9
D5
D9
T3
M3
J4
G12
1
1
1
1
PMU_TO_NAND_LOW_BATT_BOOT_L
AP_TO_NAND_FW_STRAP
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
SWD_AOP_TO_MANY_SWCLK
SWD_AP_BI_NAND_SWDIO
6
5
24
21
15
8
50
13
5
13
5
7
21
7
8
8
8
8
8
5
8
5
11
CER-X5R
20%
0201
20%
10V
C0G-CERM
01005
ROOM=NAND
20%
CER-X5R
20%
CER-X5R
20%
01005
5%
CER-X5R
0402-0.1MM
10V
01005
5%
5%
01005
C0G-CERM
CER-X5R
20%
0201
CER-X5R
4V
20%
CER-X5R
20%
6.3V
20%
6.3V
CER-X5R
0201
20%
CER-X5R
0402-0.1MM
CER-X5R
20%
CER-X5R
6.3V
6.3V
CER-X5R
0402-0.1MM
6.3V
CER-X5R
20%
X5R
0402-0.1MM
20%
X5R
0402-0.1MM
20%
X5R-CERM
6.3V
20%
1/32W
1%
40
33
31
30
29
28
18
17
15
11
9
8
7
6
20
42
40
33
31
30
29
28
18
17
15
11
9
8
7
6
20
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
EXT_D2/BOOT2/SPINAND_SCLK
EXT_NCE/PERST*
EXT_NRE/JTAG_TMS
EXT_NWE/JTAG_TCK
EXT_RNB/JTAG_TDO
EXT_CLE/JTAG_TDI
EXT_ALE/JTAG_SEL
EXT_D1/BOOT1
EXT_D0/BOOT0
EXT_D7/SPF
DROOP_N
WP_N
PCIE_REFCLK_M
PCIE_TX0_P
PCIE_TX0_M
0.80V - 0.92V
0.67V - 0.92V
BUCK0
BUCK7
13.8A MAX
2.1A MAX
2.1A MAX
1.2A MAX
#29079575: Add 22uF cap to BUCK2 and BUCK4
VOLTAGE=1.8V
VOLTAGE=1.06V
VOLTAGE=0.875V
VOLTAGE=1.06V
VOLTAGE=1.8V
VOLTAGE=1.8V
VOLTAGE=1.1V
VOLTAGE=1.01V
VOLTAGE=1.25V
VOLTAGE=0.8V
VOLTAGE=1.03V
VOLTAGE=0.8V
27 OF 80
051-02159
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C1
B6
F4
B17
E17
W18
W17
W14
H2
H1
H4
Y3
W3
V3
T4
Y9
W9
V9
Y11
W11
V11
T8
D2
D1
B2
B1
F2
F1
G4
Y7
W7
Y5
W5
T7
C9
B9
C11
B11
C13
B13
B15
A15
F15
U18
U17
R18
R17
R16
N18
N17
L18
L17
R13
1
1
1
PP1V8_TOUCH
BUCK0_FB
PP1V8_IMU_S2
BUCK1_FB
PP_GPU_SRAM
PP_DCS_S1
BUCK4_LX0
BUCK0_LX0
BUCK0_LX2
PP_CPU_PCORE
BUCK1_LX0
BUCK1_LX1
BUCK2_LX0
BUCK5_FB
BUCK3_LX0
BUCK3_FB
PP1V8_IO
PP1V8_S2
BUCK2_LX1
PP1V1_S2
BUCK6_LX0
BUCK9_LX
BUCK6_FB
BUCK9_FB
BUCK7_LX0
BUCK5_LX0
BUCK8_FB
BUCK8_LX0
BUCK7_FB
PP_CPU_SRAM
PP1V25_S2
PP0V8_SOC_FIXED_S1
BUCK4_FB
PP_GPU
BUCK1_LX2
BUCK2_FB
PP_SOC_S1
BUCK0_LX1
BUCK0_LX3
SYNC_MASTER=sync
X5R
4V
20%
4V
PIWA2012FE-SM
PIWA20160H-SM
X5R
0402-0.1MM
14
5
14
C0G-CERM
10V
4V
5%
C0G-CERM
10V
10V
01005
4V
0402-0.1MM
X5R
0402-0.1MM
20%
0402-0.1MM
4V
20%
0402-0.1MM
4V
0402-0.1MM
20%
20%
4V
0402-0.1MM
ROOM=PMU
C0G-CERM
10V
5%
X5R
20%
0402-0.1MM
4V
ROOM=PMU
4V
X5R
5%
10V
ROOM=PMU
0402-0.1MM
4V
20%
0402-0.1MM
X5R
4V
X5R
4V
X5R
0402-0.1MM
4V
20%
X5R
X5R
4V
20%
4V
5%
10V
20%
4V
20%
4V
0402-0.1MM
4V
20%
5%
10V
C0G-CERM
C0G-CERM
10V
5%
C0G-CERM
10V
X5R
X5R
0402-0.1MM
4V
0402-0.1MM
20%
X5R
0402-0.1MM
ROOM=PMU
4V
0402-0.1MM
01005
C0G-CERM
10V
4V
X5R
0402-0.1MM
X5R
4V
4V
20%
4V
0402-0.1MM
X5R
4V
42
27
14
15
14
5
42
40
33
31
30
29
28
17
15
11
9
8
7
6
50
48
47
46
45
43
41
36
25
23
21
15
13
11
5
20
15
14
28
20
15
14
10
9
8
7
14
14
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
BUCK0_LX2
BUCK0_LX0
BUCK9_FB
BUCK9_LX0
BUCK8_FB
BUCK8_LX0
BUCK7_FB
BUCK7_LX0
BUCK6_FB
BUCK6_LX0
BUCK5_FB
BUCK5_LX0
BUCK4_FB
BUCK4_LX0
BUCK3_SW3
BUCK3_SW2
BUCK3_SW1
BUCK3_FB
BUCK3_LX0
BUCK2_LX1
BUCK2_LX0
BUCK1_FB
BUCK1_LX3
BUCK1_LX2
BUCK1_LX1
BUCK1_LX0
BUCK0_FB
BUCK0_LX3
BUCK0_LX1
BUCK2_FB
VBUCK3_SW
1.2A MAX
BUCK11
VOLTAGE=0.875V
28 OF 80
051-02159
1
1
1
1
1
F14
L14
U14
R7
K5
E5
H18
B3
A3
B7
A7
C18
B18
Y17
Y16
Y15
J2
J1
Y2
W2
V2
Y10
W10
V10
E2
Y6
W6
V6
D10
C10
B10
D14
B14
T18
M18
J18
G18
G17
J15
B4
A4
E4
BUCK11_LX0
BUCK10_FB
BUCK11_LX1
BUCK11_FB
BUCK10_LX
PP_CPU_ECORE
PP0V6_VDDQL_S1
PP_VDD_MAIN
SYNC_MASTER=sync
CER-X5R
6.3V
14
6.3V
0201
0201
6.3V
0201
20%
6.3V
0201
X5R-CERM
6.3V
X5R-CERM
OMIT_TABLE
X5R-CERM
6.3V
X5R-CERM
0201
6.3V
6.3V
X5R-CERM
0201
20%
X5R-CERM
0201
20%
6.3V
0402-0.1MM
20%
6.3V
X5R-CERM
20%
X5R
0402-0.1MM
X5R
4V
ROOM=PMU
4V
X5R
20%
0402-0.1MM
20%
X5R
4V
5%
01005
C0G-CERM
5%
10V
SHORT-20L-0.05MM-SM
6.3V
0201
4V
X5R
20%
X5R-CERM
6.3V
0201
ROOM=PMU
6.3V
20%
0201
6.3V
X5R-CERM
0201
6.3V
20%
OMIT_TABLE
6.3V
0201
6.3V
0201
0201
6.3V
20%
X5R-CERM
20%
15
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
5
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
BUCK INPUT
VDD_MAIN_6
BUCK10_LX0
VDD_BUCK11
VDD_BUCK10
VDD_BUCK9
VDD_BUCK8
VDD_BUCK7
VDD_BUCK6
VDD_BUCK4
VDD_BUCK3
VDD_BUCK2
VDD_BUCK1_23
VDD_BUCK1_01
VDD_BUCK0_23
VDD_MAIN_4
VDD_MAIN_5
VDD_MAIN_2
VDD_MAIN_3
VDD_MAIN_1
VDD_MAIN_SNS
BUCK11_LX0
BUCK10_FB
BUCK11_LX1
BUCK11_FB
LDO14
LDO13
LDO12
LDO11
LDO10
LDO8
LDO5
LDO3
LDO2
LDO1
LDO7
LDO9
VBUF_1V2
LDO4
VOLTAGE=3.0V
VOLTAGE=1.8V
VOLTAGE=1.2V
VOLTAGE=3.3V
VOLTAGE=1.8V
VOLTAGE=2.5V
VOLTAGE=1.8V
VOLTAGE=0.7V
VOLTAGE=3.0V
VOLTAGE=0.9V
VOLTAGE=3.3V
VOLTAGE=3.0V
VOLTAGE=1.2V
VOLTAGE=1.2V
29 OF 80
051-02159
1
1
1
Y4
Y12
Y1
V17
V16
U3
U15
R15
P9
P10
N9
K17
K16
K14
J5
J16
J13
H5
H3
H16
G5
G16
G1
F5
F18
E3
E18
D9
D18
C8
C7
C6
C17
C12
B8
B5
B16
A8
A18
A1
E14
T2
P4
P6
N6
P2
L2
U1
N2
M5
T1
R3
L4
R4
M6
R2
M1
L1
W1
V1
N1
M4
N4
K4
K1
J4
K2
N5
T14
1
1
1
PP_VDD_MAIN
PP_VDD_BOOST
PMU_VSS_RTC
PP1V1_S2
OMIT_TABLE
X5R-CERM
6.3V
X5R-CERM
20%
18
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
50
43
41
36
28
22
20
21
18
15
50
43
41
36
28
22
20
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
20
17
33
24
21
36
7
43
20
39
38
37
36
14
50
48
47
46
44
33
5
17
47
45
43
15
14
10
8
15
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VSS
PMU_TO_BT_REG_ON
PMU_TO_GNSS_EN
NFC_TO_PMU_HOST_WAKE
WLAN_TO_PMU_HOST_WAKE
SYNC_DATE=04/14/2017
34
47
41
7
01005
01005
X5R-CERM
0%
MF
01005
SHORT-20L-0.05MM-SM
21
42
41
10V
10%
X5R
5
11
5
50
21
MF
1/32W
1%
01005
MF
0201-1
20%
50
36
MF
01005
5
50
17
19
14
20
45
41
21
25
22
25
X5R
7
46
50
50
12
12
7
7
12
7
50
50
50
34
34
47
21
20
14
5
14
5
29
21
45
41
11
45
41
21
11
5
5
13
24
21
17
15
13
21
7
50
21
47
21
12
7
11
50
42
29
22
13
7
5
47
7
1/32W
5%
01005
5%
20%
X5R
1/20W
1%
MF
6.3V
X5R
NP0-C0G
01005
16V
5%
1/20W
0.1%
0201
01005
ROOM=B2B_WIDE_RCAM
NP0-C0G
01005
5%
NP0-C0G
01005
NP0-C0G
5%
47
12
5
24
21
17
15
50
50
48
47
46
45
43
41
36
25
23
18
15
13
11
5
21
7
41
21
29
21
24
20
20
21
21
21
21
40
21
21
21
40
21
40
21
21
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
CLKOUT
GND
NC
XTAL
REFS
BUTTONS
AMUX
GPIO
NTC
Otherwise tracks VDD_MAIN
31 OF 80
051-02159
1
B4
B3
A4
C4
C2
B2
D3
A1
C1
1
1
PP_VDD_BOOST
PP_VDD_MAIN
I2C0_SMC_SCL
PMU_TO_BOOST_EN
SYS_BOOST_LX
I2C0_SMC_SDA
SYNC_MASTER=sync
5%
C0G-CERM
0402-0.1MM
20%
X5R
6.3V
20%
X5R
6.3V
01005
MF
1/32W
25
24
23
11
46
25
24
23
11
50
42
29
21
13
X5R
6.3V
20%
X5R
6.3V
20%
X5R
6.3V
43
41
36
28
20
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
20
19
5
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
AGND
PGND
SCL
BYP*
EN
SW
VOUT
SW
GPIO
SDA
VSEL
�THIS ONE ON MLB ---
Gas gauge I2C level translator
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
D
D
10V
01005
CERM
0402-0.1MM
CERM
6.3V
20%
01005
01005
10V
21
7
47
5
21
17
15
46
25
23
22
11
46
25
23
22
11
1/32W
MF
01005
10%
0201
X5R
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
S
D
110 RESERVED FOR OTHER PROGRAMS
G5
E7
H6
L6
J5
K7
H4
H5
K4
J7
K3
L3
J4
A2
A5
A6
L4
J2
K2
G7
E3
H7
F7
E6
E5
F1
H1
J1
D1
D2
F3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
K
2
2
2
2
2
2
1
2
1
2
5
24
5
26
5
26
25
5
19
20
22
24
25
28
32
37
38
39
40
41
42
44
45
47
48
50
5
19
20
22
24
25
28
32
37
38
39
40
41
42
44
45
47
48
50
25
11
25
5
11
13
15
18
21
23
36
41
43
45
46
47
48
50
25
5
19
20
22
24
25
28
32
37
38
39
40
41
42
44
45
47
48
50
25
25
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
AC1
AC1
BOOT2_VDD
COMM2
CLAMP2
GPIO3/SWDIO
VMID_AUX_SW_VDD
SW
OTP_WREN
AC1
AC2
AC2
AC2
COMM1
VDIG_CORE_VDD
VDD5V
SDA
SCL
INT
#31690340:Remove XWs on Iktara Coil Paths
10.0.0
35 OF 80
051-02159
11
10
9
8
7
6
5
4
3
2
1
1
IKTARA_COIL1_CONN
SYNC_DATE=04/14/2017
ROOM=B2B_CYCLONE
0201
50V
2%
220PF
50V
0201
C0G
0201
2%
220PF
50V
0201
5
25
5
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
114K INT PD
114K INT PU
10.0.0
36 OF 80
051-02159
8
3
4
7
1
16
2
7
3
4
6
13
12
9
1
1
1
1
1
1
B4
A4
D2
D1
B3
D4
A1
A2
SPI_AOP_TO_IMU_SCLK
PP1V8_IMU_S2
PP1V8_IMU_S2
SPI_IMU_TO_AOP_MISO
PP1V8_IMU_S2
SPI_AOP_TO_IMU_MOSI
SPI_AOP_TO_IMU_SCLK
SPI_AOP_TO_COMPASS_CS_L
PP1V8_IMU_S2
SPI_AOP_TO_IMU_MOSI
COMPASS_TO_AOP_INT
SPKRAMP_TOP_TO_COIL_OUT_POS
ACCEL_GYRO_TO_AOP_DATARDY
ACCEL_GYRO_TO_AOP_INT
SPI_IMU_TO_AOP_MISO
SPI_IMU_TO_AOP_MISO
SPKRAMP_TOP_TO_COIL_OUT_NEG
SPI_AOP_TO_IMU_MOSI
SPI_AOP_TO_IMU_SCLK
PHOSPHORUS_TO_AOP_INT
SPI_AOP_TO_ACCEL_GYRO_CS_L
SYNC_DATE=04/14/2017
1/32W
1%
01005
1/32W
1%
01005
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
SDI
SDO
VDD
VDDIO
IRQ
GND
SCK
INT
SM
MOTION_INT
VDDIO
MOSI
GND
GND
GND
GND
RSV
RSV
RSV
VDD
VSS
SDO
SCL/SCK
SDA/SDI
CSB
TRG/SE
DRDY
RSV
RST*
C LDO4: 300mA max
CX LDO9: 390mA max
D LDO15: 400mA max
Actual Load: 390mA
C LDO20: 300mA max
D LDO18: 400mA max
C LDO17: 300mA max
C LDO21: 300mA max
C LDO19: 300mA max
Ga LDO10: 1300mA max
#31710713:C3704 to 4UF to mitigate RnR
/1.95V
#32596057:Increase C3722 to 3.9UF to Help RCAM ONZ
VOLTAGE=2.85V
VOLTAGE=2.6V
VOLTAGE=1.8V
VOLTAGE=2.85V
VOLTAGE=1.15V
VOLTAGE=1.15V
VOLTAGE=1.15V
VOLTAGE=2.85V
VOLTAGE=2.6V
VOLTAGE=3.3V
37 OF 80
051-02159
1
1
1
1
1
G1
B7
B8
A3
A4
B1
A5
A6
J2
B2
H1
A8
A7
B3
B4
B5
B6
H2
A2
A1
H3
F2
J3
E2
C5
J8
J7
H8
H5
PP_VDD_MAIN
PP2V85_VAR_CAM_VCM_PVDD
CAMPMU_BUCK_LX0
PP1V8_IO
PP_VDD_BOOST
CAMPMU_ON_BUF
PP1V25_S2
CAMPMU_BUCK_FB
PP_CAM_WIDE_ADC
PP1V8_HAWKING
PP2V85_CAM_WIDE_AVDD
PP1V1_CAM_TELE_DVDD
PP1V1_FCAM_DVDD
PP1V1_CAM_WIDE_DVDD
PP2V85_CAM_TELE_AVDD
PP_CAM_TELE_ADC
PP3V3_SVDD
SYNC_DATE=04/14/2017
6.3V
X5R-CERM
0201
CER-X5R
0201
X5R-CERM
6.3V
6.3V
20%
0201
6.3V
01005
16V
6.3V
X5R-CERM
6.3V
0201
X5R-CERM
20%
0201
X5R-CERM
0201
6.3V
20%
CER-X5R
6.3V
6.3V
X5R-CERM
6.3V
6.3V
0201
CER-X5R
6.3V
6.3V
X5R-CERM
X5R
6.3V
20%
CER-X5R
X5R-CERM
6.3V
0201
20%
6.3V
0201
6.3V
20%
CER-X5R
50
48
47
45
44
42
41
40
39
38
37
32
25
24
22
20
19
5
30
42
40
33
31
30
29
18
17
15
11
9
8
7
6
50
43
41
36
22
20
20
18
30
34
30
31
33
30
31
31
31
30
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
SW INPUT
SYM 2 OF 4
LDO OUTPUT
LDO INPUT
VLDO4
VLDO15
VLDO18
VLDO17
VLDO20
VLDO19
VLDO22
VLDO21
ON_BUF
BUCK3_SW1
VDD_LDO9
VDD_LDO4_17
VDD_LDO19
VDD_LDO18
VDD_LDO20_21
VDD_LDO22
VDD_LDO20_21
VDD_LDO10
VDD_LDO15
VBUCK3
VPUMP
SYM 1 OF 4
VCC MAIN
VDD_MAIN
VDD_MAIN
VDD_MAIN
VDD_BUCK9
BUCK9_LX0
BUCK9_LX0
BUCK9_FB
#29220631: Connect Neon to other side of R3802 and change to 49.9 ohms
38 OF 80
051-02159
1
1
1
1
1
1
J6
J1
H4
G8
F1
E5
D5
C7
C4
C1
G5
J5
C6
F8
E8
F5
D8
D1
E3
G2
F3
F7
D6
E7
C8
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
REFERENCE
#27431370
516S00310/P2 RCPT (USED ON MLB)
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
39 OF 80
051-02159
1
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
90_LPDP_WIDE_TO_AP_D1_N
90_LPDP_WIDE_TO_AP_D1_P
WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
PP_CAM_WIDE_ADC
PP1V1_CAM_WIDE_DVDD_CONN
LPDP_WIDE_BI_AP_AUX_CONN
90_LPDP_WIDE_TO_AP_D2_CONN_P
PP3V3_SVDD
PP1V1_CAM_WIDE_DVDD_CONN
PP_CAM_VCM_PVDD_CONN
PP2V85_VAR_CAM_VCM_PVDD
PP1V1_CAM_WIDE_DVDD
PP1V1_CAM_WIDE_DVDD_CONN
90_LPDP_WIDE_TO_AP_D0_CONN_N
90_LPDP_WIDE_TO_AP_D2_P
90_LPDP_WIDE_TO_AP_D0_P
WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE
WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
I2C0_ISP_SCL
90_LPDP_WIDE_TO_AP_D2_CONN_P
I2C0_ISP_TO_WIDE_RCAM_OIS_SCL_CONN
LPDP_WIDE_BI_AP_AUX_CONN
LPDP_WIDE_BI_AP_AUX
90_LPDP_WIDE_TO_AP_D2_N
90_LPDP_WIDE_TO_AP_D2_CONN_N
90_LPDP_WIDE_TO_AP_D1_CONN_N
90_LPDP_WIDE_TO_AP_D1_CONN_P
90_LPDP_WIDE_TO_AP_D0_N
PP_CAM_VCM_PVDD_CONN
PP1V8_IO
PP_CAM_WIDE_ADC
PP_CAM_VCM_PVDD_CONN
90_LPDP_WIDE_TO_AP_D1_CONN_N
PP1V8_CAM_WIDE_VDDIO_CONN
WIDE_TO_TELE_SYNC_J3900_CONN
I2C0_ISP_TO_WIDE_RCAM_OIS_SCL_CONN
AP_TO_WIDE_CLK_CONN
90_LPDP_WIDE_TO_AP_D0_CONN_P
PP3V3_SVDD
ISP_TO_WIDE_SHUTDOWN_CONN_L
I2C0_ISP_BI_WIDE_RCAM_OIS_SDA_CONN
90_LPDP_WIDE_TO_AP_D0_CONN_N
90_LPDP_WIDE_TO_AP_D1_CONN_P
PP2V85_CAM_WIDE_AVDD
PP1V8_CAM_WIDE_VDDIO_CONN
AP_TO_WIDE_CLK
I2C0_ISP_SDA
I2C0_ISP_BI_WIDE_RCAM_OIS_SDA_CONN
ISP_TO_WIDE_SHUTDOWN_L
AP_TO_WIDE_CLK_CONN
SYNC_MASTER=sync
X5R-CERM
6.3V
20%
X5R-CERM
6.3V
20%
X5R-CERM
6.3V
20%
X5R-CERM
6.3V
C0G-CERM
01005
5%
C0G-CERM
10V
0%
MF
MF
1/32W
MF
5%
01005
16V
01005
5%
X5R-CERM
6.3V
X5R-CERM
6.3V
X5R-CERM
6.3V
C0G-CERM
10V
X5R-CERM
6.3V
10V
01005
5%
10V
01005
10V
01005
C0G-CERM
10V
C0G-CERM
10V
32
9
9
9
9
10
10
10
10
10
10
X5R-CERM
6.3V
X5R-CERM
6.3V
0%
1/32W
01005
ROOM=B2B_WIDE_RCAM
5%
NP0-C0G-CERM
NP0-C0G-CERM
25V
5%
0%
01005
20%
6.3V
NP0-C0G-CERM
5%
31
30
30
28
30
30
30
31
30
28
30
30
28
30
28
28
30
30
31
30
30
30
30
30
30
30
30
30
42
40
33
31
29
28
18
17
15
11
9
8
7
6
30
28
30
30
30
31
30
30
30
30
31
30
28
30
30
30
30
30
28
30
30
30
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
Tele Camera Connector
516S00309/P2 PLUG (USED ON FLEX)
�THIS ONE ---
#29487888
#27431370
Power Filtering
LPDP
CKPLUS_WAIVE=I2C_PULLUP
40 OF 80
051-02159
1
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I2C1_ISP_BI_TELE_SDA_CONN
PP1V1_CAM_TELE_DVDD_CONN
90_LPDP_TELE_TO_AP_D2_CONN_N
90_LPDP_TELE_TO_AP_D2_CONN_P
AP_TO_TELE_CLK_CONN
PP2V85_CAM_TELE_AVDD
PP_CAM_TELE_ADC
PP1V8_CAM_TELE_VDDIO_CONN
PP1V1_CAM_TELE_DVDD_CONN
PP3V3_SVDD
PP1V8_CAM_TELE_VDDIO_CONN
WIDE_TO_TELE_SYNC_J4000_CONN
ISP_TO_TELE_SHUTDOWN_CONN_L
LPDP_TELE_BI_AP_AUX_CONN
90_LPDP_TELE_TO_AP_D1_CONN_P
WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
90_LPDP_TELE_TO_AP_D0_N
90_LPDP_TELE_TO_AP_D1_P
PP2V85_CAM_TELE_AVDD
PP1V8_CAM_TELE_VDDIO_CONN
PP1V8_IO
PP3V3_SVDD
WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
WIDE_TO_TELE_SYNC_J3900_CONN
WIDE_TO_TELE_SYNC_J4000_CONN
LPDP_TELE_BI_AP_AUX
90_LPDP_TELE_TO_AP_D2_CONN_N
90_LPDP_TELE_TO_AP_D2_N
90_LPDP_TELE_TO_AP_D2_CONN_P
90_LPDP_TELE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D1_CONN_N
90_LPDP_TELE_TO_AP_D1_CONN_P
90_LPDP_TELE_TO_AP_D0_CONN_P
90_LPDP_TELE_TO_AP_D0_P
LPDP_TELE_BI_AP_AUX_CONN
PP1V1_CAM_TELE_DVDD
PP_CAM_TELE_ADC
I2C1_ISP_SDA
I2C1_ISP_SCL
I2C1_ISP_BI_TELE_SDA_CONN
90_LPDP_TELE_TO_AP_D1_N
90_LPDP_TELE_TO_AP_D0_CONN_N
AP_TO_TELE_CLK
AP_TO_TELE_CLK_CONN
90_LPDP_TELE_TO_AP_D0_CONN_P
I2C1_ISP_TO_TELE_SCL_CONN
90_LPDP_TELE_TO_AP_D1_CONN_N
ISP_TO_TELE_SHUTDOWN_L
SYNC_MASTER=sync
0%
01005
C0G-CERM
10V
ROOM=B2B_TELE_RCAM
0%
01005
1/32W
MF
01005
01005
C0G-CERM
5%
X5R
20%
X5R-CERM
0201
01005
16V
NP0-C0G-CERM
0201
10V
01005
C0G-CERM
01005
C0G-CERM
10V
01005
10
10
10
10
10
30
31
30
9
9
9
9
X5R-CERM
20%
01005
X5R-CERM
20%
01005
X5R-CERM
20%
5%
01005
NP0-C0G-CERM
1/32W
MF
0%
ROOM=B2B_TELE_RCAM
01005
NP0-C0G-CERM
25V
01005
25V
0%
MF
1/32W
X5R-CERM
20%
01005
X5R-CERM
20%
01005
X5R-CERM
20%
01005
X5R-CERM
20%
NP0-C0G-CERM
25V
01005
01005
C0G-CERM
10V
01005
10V
C0G-CERM
C0G-CERM
31
31
31
31
31
31
28
28
31
31
31
30
28
31
31
31
31
31
30
31
28
31
42
40
33
30
29
28
18
17
15
11
9
8
7
6
31
30
28
31
31
31
31
31
31
31
31
28
31
28
31
31
31
31
31
31
31
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
APN:353S00558
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND1
GND2S
GND1S
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
LED1
LED2
LED2
NTC
VDD
VDD
VDD
HWEN0
SDA2
GSM0
STB0
SCL2
LED1
LED2
LED1
LED2
NTC
VDD
VDD
VDD
GSM1
SDA1
STB1
SCL1
MIC3
FOREHEAD CONNECTOR
CONVOY I/O
FCAM POWER
R4287/R4288 to 100ohm to reduce Xtalk
#30299013:Stuff 100pF at C4287/C4288
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
42 OF 80
051-02159
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
42
41
40
39
38
37
1
1
1
1
1
1
1
1
1
1
ISP_TO_FCAM_SHUTDOWN_CONN_L
SPKRAMP_TOP_TO_COIL_OUT_NEG
I2C2_AP_BI_CONVOY_SDA_CONN
PDM_CONVOY_TO_SPKRAMP_TOP_DATA_CONN
COIL_TO_SPKRAMP_TOP_VSENSE_CONN_P
I2C0_AOP_TO_PROX_ALS_SCL_CONN
PP_CODEC_TO_FRONTMIC3_BIAS_CONN
NP0-C0G-CERM
01005
01005
25V
01005
MF
1/32W
01005
0%
MF
25V
01005
NP0-C0G-CERM
5%
25V
MF
01005
MF
1/32W
5%
6.3V
20%
10V
5%
C0G-CERM
6.3V
X5R-CERM
0201
C0G-CERM
01005
01005
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
MIC2 (ANC REF)
HAWKING
Strobe Filtering
Strobe Connector
43 OF 80
051-02159
1
1
1
1
1
1
1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I2C1_AP_BI_MIC2_SDA
PP_STROBE_DRIVER1_WARM_LED
BUTTON_VOL_DOWN_CONN_L
BUTTON_POWER_KEY_L
PP1V8_HAWKING
CHASSIS_GND_BS401
REARMIC2_TO_CODEC_AIN2_P
REARMIC2_TO_CODEC_AIN2_N
I2C1_AP_SDA
HAWKING_TO_CODEC_AIN5_C_P
BUTTON_VOL_DOWN_L
HAWKING_TO_CODEC_AIN5_N
HAWKING_TO_CODEC_AIN5_N_CONN
HAWKING_TO_CODEC_AIN5_P
BUTTON_VOL_UP_L
HAWKING_TO_CODEC_AIN5_P_CONN
HAWKING_TO_CODEC_AIN5_N_CONN
HAWKING_TO_CODEC_AIN5_P_CONN
BUTTON_VOL_DOWN_CONN_L
PP_STROBE_DRIVER1_COOL_LED
PP_STROBE_DRIVER2_WARM_LED
BUTTON_VOL_UP_CONN_L
BUTTON_RINGER_A_CONN
BUTTON_POWER_KEY_CONN_L
PP_STROBE_DRIVER2_COOL_LED
PP1V8_HAWKING_CONN
STROBE_MODULE_NTC_CONN
STROBE_MODULE_NTC
STROBE_MODULE_NTC_CONN
PP_STROBE_DRIVER2_COOL_LED
I2C1_AP_SCL
BUTTON_RINGER_A
BUTTON_RINGER_A_CONN
I2C1_AP_TO_MIC2_SCL
PP_CODEC_TO_REARMIC2_BIAS_CONN
PP_STROBE_DRIVER2_WARM_LED
PP_STROBE_DRIVER1_COOL_LED
PP_STROBE_DRIVER1_WARM_LED
34
34
32
34
21
28
34
4
34
4
36
34
4
34
34
4
34
21
34
21
34
34
34
34
34
32
34
32
34
34
34
34
32
34
34
32
21
34
34
34
32
34
32
34
32
36
34
34
34
34
34
34
34
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
10.0.0
47 OF 80
051-02159
1
F10
B9
A10
B10
B11
G1
E1
F1
F8
E9
D9
D10
E10
E11
D8
B8
K8
L8
C2
D3
F4
E3
F3
G4
G3
G2
K5
L5
K6
L6
K4
L4
K3
L3
1
1
1
1
LOWERMIC1_TO_CODEC_AIN1_P
LOWERMIC1_TO_CODEC_AIN1_N
REARMIC2_TO_CODEC_AIN2_P
REARMIC2_TO_CODEC_AIN2_N
FRONTMIC3_TO_CODEC_AIN3_N
LOWERMIC4_TO_CODEC_AIN4_P
HAWKING_TO_CODEC_AIN5_P
HAWKING_TO_CODEC_AIN5_N
PDM_CODEC_TO_SPKRAMP_TOP_CLK
PDM_CODEC_TO_ARC_CLK
PDM_CODEC_TO_ARC_DATA
LOWERMIC4_TO_CODEC_AIN4_N
90_MIKEYBUS_CODEC_DATA_P
MIKEYBUS_REFERENCE
90_MIKEYBUS_DATA_P
90_MIKEYBUS_DATA_N
PDM_CODEC_TO_SPKRAMP_TOP_DATA
SYNC_MASTER=sync
5%
MF
1/32W
01005
ROOM=CODEC
1/32W
5%
16V
NP0-C0G
34
39
39
48
47
47
38
38
33
34
34
48
48
48
48
1/32W
MF
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
AOUT+
AIN3+
MBUS_REF
DN
DP
AIN1+
AIN1-
AIN2+
AIN2-
AIN3-
AIN4+
AIN5+
AIN5-
AIN6+
AIN6-
AIN7+
AIN7-
AIN8+
AIN8-
DMIC1_CLK
DMIC1_DATA
DMIC3_DATA
DMIC2_CLK
DMIC3_CLK
DMIC2_DATA
DMIC4_CLK
DMIC4_DATA
PDMOUT1_CLK
PDMOUT1_DATA
PDMOUT2_CLK
PDMOUT2_DATA
PDMOUT3_CLK
PDMOUT3_DATA
AIN4-
#30638490: Route U1000/U5000 ASP1 BCLK, LRCLK with _R
VOLTAGE=2.86V
VOLTAGE=2.86V
VOLTAGE=2.86V
48 OF 80
051-02159
1
1
1
1
1
1
1
J5
J3
G10
B2
B3
C3
A3
J4
C8
B7
A5
B4
A4
E7
F7
E8
D4
E5
E4
H2
H1
H4
H5
C7
F6
A7
D11
C10
C11
C9
C5
D6
C4
D5
B6
B5
A6
C6
L9
A2
A9
G11
B1
C1
K2
J2
H10
H8
J9
K9
J10
K10
D1
D2
L10
L7
K7
F11
E2
A11
A8
L2
1
1
1
1
1
AOP_TO_CODEC_CLP_EN
CODEC_TO_AOP_GPIO2
CODEC_TO_AOP_GPIO1
CODEC_FILTP
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
I2S_CODEC_ASP2_TO_AOP_DIN
I2S_AP_TO_CODEC_ASP3_DOUT
I2S_CODEC_ASP3_TO_AP_DIN
I2S_AP_TO_CODEC_ASP3_LRCLK
I2S_AP_TO_CODEC_ASP3_BCLK
I2S_AOP_TO_CODEC_ASP2_DOUT
I2S_AOP_TO_CODEC_ASP2_LRCLK
20%
0201-1
6.3V
0201-1
6.3V
20%
0201-1
X5R
6.3V
20%
0201-1
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
50
43
41
28
22
20
20
36
39
38
37
20
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
33
34
48
48
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GNDA
TSTI
TSTI
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
GNDA
FILT+
LP_FILT-
LP_FILT+
VA
VA
VP
VD_FILT
VD_FILT
VL
VD
VL_SW
MIC1_BIAS_FILT
GNDD
MIC2_BIAS_FILT
MIC5_BIAS
MIC5_BIAS_FILT
MIC4_BIAS
MIC4_BIAS_FILT
MIC6_BIAS_FILT
MIC6_BIAS
MIC3_BIAS
MIC3_BIAS_FILT
MIC1_BIAS
GNDP
I2C ADDRESS: 1000 000x
0x80
VOLTAGE=8.0V
VOLTAGE=8.0V
49 OF 80
051-02159
N4
M4
P2
N2
1
E3
A1
D1
C1
B6
D7
D6
C7
E6
A6
D5
E7
F7
D2
C2
B7
C6
F1
A7
D3
B4
F2
E4
F6
F3
E5
1
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
PP_SPKRAMP_BOT_VBOOST
SPKRAMP_BOT_ISENSE_P
COIL_TO_SPKRAMP_BOT_VSENSE_P
PP_VDD_MAIN
SPKRAMP_BOT_ARC_TO_AOP_INT_L
I2C1_AOP_SDA
SPKRAMP_BOT_ISENSE_N
COIL_TO_SPKRAMP_BOT_VSENSE_N
SPKRAMP_BOT_FILT
CODEC_TO_SPKRAMP_BOT_ARC_MCLK
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
SPK
VDD_S
PDM_CLK0
AD0/PDM_CLK1
VBST_A
SW
SW
FILT+
GNDP
GNDA
ISNS+
ISNS-
VSNS+
VSNS-
OUT+
OUT-
VBST_A
VBST_B
VBST_B
SDA
ALIVE/SYNC
MCLK
SCLK
LRCK/FSYNC
SDOUT
SCL
VA
PDM_DATA0
PDM_DATA1
AD1
INT*
I2C ADDRESS: 1000 000x (0x80)
VOLTAGE=8.0V
VOLTAGE=8.0V
50 OF 80
051-02159
1
1
E3
A1
D1
C1
B6
D7
D6
C7
E6
A6
D5
E7
F7
D2
C2
B7
C6
F1
A7
D3
C3
B4
B3
F2
E4
F6
F3
E5
1
1
COIL_TO_SPKRAMP_TOP_VSENSE_N
SPKRAMP_TOP_ISENSE_P
SPKRAMP_TOP_ISENSE_N
SPKRAMP_TOP_FILT
COIL_TO_SPKRAMP_TOP_VSENSE_P
SPKRAMP_TOP_TO_COIL_OUT_POS
PP1V8_AUDIO_VA_S2
PP_SPKRAMP_TOP_VBOOST
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
PDM_CONVOY_TO_SPKRAMP_TOP_DATA
SPKRAMP_TOP_TO_AP_INT_L
PDM_SPKRAMP_TOP_TO_CONVOY_CLK
PDM_SPKRAMP_TOP_TO_CONVOY_CLK
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
PDM_CLK0
AD0/PDM_CLK1
VBST_A
SW
SW
FILT+
GNDP
GNDA
ISNS+
ISNS-
VSNS+
VSNS-
OUT+
OUT-
VBST_A
VBST_B
VBST_B
SDA
ALIVE/SYNC
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
SCL
VA
PDM_DATA0
PDM_DATA1
AD1
INT*
APN: 338S00295
VOLTAGE=8.0V
51 OF 80
051-02159
1
1
E3
A1
D1
C1
B6
D7
D6
C7
E6
A6
D5
E7
F7
D2
C2
B7
C6
F1
A7
D3
C3
B4
B3
F2
E4
F6
F3
E5
1
1
1
ARC1_ISENSE_N
ARC1_FILT
ARC1_TO_SOLENOID1_OUT_NEG
ARC1_TO_SOLENOID1_OUT_POS
CODEC_TO_SPKRAMP_BOT_ARC_MCLK
PDM_CODEC_TO_ARC_DATA
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
PDM_CODEC_TO_ARC_CLK
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
PP1V8_AUDIO_VA_S2
I2C1_AOP_SDA
PP1V8_AUDIO_VA_S2
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
PDM_CLK0
AD0/PDM_CLK1
VBST_A
SW
SW
FILT+
GNDP
GNDA
ISNS+
ISNS-
VSNS+
VSNS-
OUT+
OUT-
VBST_A
VBST_B
VBST_B
SDA
ALIVE/SYNC
MCLK
SCLK
LRCK/FSYNC
SDOUT
SCL
VA
PDM_DATA0
PDM_DATA1
AD1
INT*
See pages 49, and 56
CKPLUS_WAIVE=I2C_PULLUP
55 OF 80
051-02159
AE4
AD4
AD1
Y7
Y6
V1
U7
R3
R2
N5
N3
N1
M7
L7
L6
L5
K7
J7
J4
J1
H7
G7
F7
F5
F4
E7
D7
D1
C7
B7
AD7
AE6
AC7
A2
C1
A1
A3
N6
R6
U6
U5
AB6
AB5
AD3
AB3
AA3
AA2
Y3
W3
V3
U3
T3
CHARGER_NTC
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND2_SR_TOP_SNS2
GND2_SR_TOP_SNS1
GND2_SR_TOP_FRC1
GND1_SR_TB_FRC2
GND1_SR_TB_SNS2
GND1_SR_TB_SNS1
GND1_SR_TB_FRC1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_18
TIG_MID
TIGRIS_LX6
TIGRIS_LX7
TIGRIS_LX3
TIGRIS_LX4
TIGRIS_LX1
TIGRIS_LX2
TIGRIS_LX0
TIG_MID
TIG_MID
VDD_T
VDD_T
TIG_MID
VDD_T
VDD_T
VDD_T
VDD_T
TIG_MID
TIG_MID
TIG_MID
TIG_MID
TIG_MID
TIG_MID
TIG_MID
TIG_MID
TIG_MID
APN:152S00248/152S00603 (12.5UH-15%-1.1A-0.66OHM)
APN:152S00248/152S00603 (12.5UH-15%-1.1A-0.66OHM)
4LED
NO INT PULL
NO INT PULL
APN:353s00640
VOLTAGE=6.0V
VOLTAGE=17.0V
VOLTAGE=5.1V
VOLTAGE=5.7V
56 OF 80
051-02159
E2
D3
C2
B3
B2
E6
C5
B6
J3
H3
H2
G3
G2
K6
H5
G6
1
1
1
1
1
A2
B1
C1
A3
B2
1
D1
A4
A3
C4
C2
B2
A2
C3
A1
B1
C1
D2
D4
B3
K
1
A
1
1
A
K
D1
A4
A3
C4
C2
B2
A2
C3
A1
B1
C1
D2
D4
B3
1
1
1
E3
D1
A2
D2
D3
C2
B1
C3
A1
A3
A4
B4
E4
C4
1
PP_CHESTNUT_CP
PP_VDD_MAIN
I2C0_AP_SCL
DISPLAY_TO_CHESTNUT_PWR_EN
I2C0_AP_SDA
I2C3_AP_SDA
PP_DISPLAY_BL34_CAT2
PP_DISPLAY_BL34_CAT1
I2C0_AP_SDA_CHESTNUT_R
PP1V8_S2
DWI_PMGR_TO_BACKLIGHT_DATA
DWI_PMGR_TO_BACKLIGHT_CLK
I2C0_AP_SCL
AP_TO_MUON_BL_STROBE_EN
BB_TO_STROBE_DRIVER_GSM_BURST_IND
PP16V0_MESA
PP17V0_MOJAVE_LDOIN
PP_VDD_MAIN
MESA_TO_BOOST_EN
CHESTNUT_TO_PMU_AMUX
PP_VDD_BOOST
POS18V0_MESA_LX
DWI_PMGR_TO_BACKLIGHT_CLK
DWI_PMGR_TO_BACKLIGHT_DATA
BB_TO_STROBE_DRIVER_GSM_BURST_IND
AP_TO_MUON_BL_STROBE_EN
BL12_SW2_LX
PP_DISPLAY_BL12_CAT1
PP_DISPLAY_BL34_ANODE
PP6V0_DISPLAY_BOOST
CHESTNUT_LX
I2C0_AP_SDA_CHESTNUT_R
BL34_SW1_LX
BL12_SW1_LX
PP_VDD_MAIN
BL34_SW2_LX
PP_DISPLAY_BL12_CAT2
I2C3_AP_SCL
PP1V8_S2
PP_VDD_MAIN
PP_DISPLAY_BL12_ANODE
PMU_TO_AP_HYDRA_ACTIVE_READY
PP5V1_TOUCH_VDDH
PP5V7_DISPLAY_AVDDH
PN5V7_DISPLAY_MESON_AVDDN
SYNC_MASTER=sync
X5R-CERM
0402-0.1MM
ROOM=CHESTNUT
20%
10V
X5R-CERM
20%
0402
50
41
32
41
9
45
41
21
11
41
11
5
41
11
5
48
42
48
42
11
50
41
32
41
9
41
11
5
41
11
5
21
47
21
7
42
21
45
21
11
45
41
21
11
5%
01005
MF
ROOM=MOJAVE
6.3V
0201
CERM
0402-0.1MM
6.3V
ROOM=MOJAVE
25V
5%
01005
01005
COG
35V
20%
20%
X5R
0402-0.1MM
20%
6.3V
COG
25V
01005
PLACE_NEAR=U5660:2MM
ROOM=BACKLIGHT
X5R
0402
35V
20%
0402
X5R
X5R
35V
ROOM=BACKLIGHT
X5R
0402
35V
X5R
0402
20%
ROOM=BACKLIGHT
35V
X5R
X5R
35V
0402
35V
20%
X5R
20%
0402
35V
MF
1%
01005
15UF
CERM
20%
0402-0.1MM
5%
COG
6.3V
20%
10V
01005
CER-X5R
0201
10UF
20%
10V
0402-0.1MM
10V
X5R-CERM
10V
20%
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
42
42
41
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
43
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
50
43
36
28
22
20
42
42
41
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
42
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
42
42
42
42
42
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VDD34
VDD34
VDD34
VDD34
VDD34
VDD34
VDD34
BL34
BL34
BL34
BL34
BL34
VDD12
VDD12
VDD12
VDD12
VDD12
VDD12
BL12
BL12
BL12
BL12
BL12
VOUT
EN_S
LDOIN
EN_M
AGND
VIO/HWEN
SCK
SDA
TRIG
SW2_1
SW2_2
SCL
SW1
IN
OUT
LED1
LED2
INHIBIT
GND
VIO/HWEN
SCK
SDA
TRIG
SW2_1
SW2_2
SCL
SW1
IN
OUT
LED1
LED2
INHIBIT
GND
HVLDO2
HVLDO1
PGND2
PGND1
LCMBST
CF2
ADCMUX
#27428158:Ground J5700.12
1/32W
10V
X5R
10%
0201
X5R-CERM
6.3V
X5R-CERM
10V
01005
25V
5%
25V
5%
ROOM=B2B_DISPLAY
5%
COG
25V
COG
25V
5%
5%
25V
COG
NP0-C0G-CERM
5%
10V
5%
41
48
43
42
43
9
9
9
9
9
9
9
9
9
9
12
11
11
11
11
12
13
13
21
22
29
50
11
41
48
21
12
21
41
10V
5%
10V
C0G-CERM
5%
1%
MF
1%
MF
1%
1/20W
MF
1/20W
0201
MF
1%
1%
1/20W
MF
SYNC_DATE=04/14/2017
PP1V8_TOUCH
TOUCH_TO_AOP_GPO_CONN
PP5V7_DISPLAY_AVDDH_CONN
PN5V7_DISPLAY_MESON_AVDDN_CONN
I2C_DISP_EEPROM_SCL_CONN
PN5V7_DISPLAY_MESON_AVDDN
PP_DISPLAY_BL34_CAT1
PP_DISPLAY_BL34_ANODE
PP_DISPLAY_BL12_CAT2
PP_DISPLAY_BL12_ANODE
I2C3_AP_SDA
I2C3_AP_SCL
PMU_TO_DISPLAY_PANICB
I2C_DISP_EEPROM_SCL_CONN
PP5V7_MESON_AVDDH
2
2
2
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
54
2
2
2
3
4
2
3
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
2
2
2
42
5
42
18
42
43
42
42
42
42
41
41
41
41
41
42
41
5
42
5
42
42
42
42
42
6
7
8
9
11
15
17
18
28
29
30
31
33
40
41
42
41
18
42
43
42
43
42
42
43
42
42
42
42
42
42
5
19
20
22
24
25
28
32
37
38
39
40
41
44
45
47
48
50
42
42
5
42
5
42
5
42
5
42
5
42
5
42
42
42
42
42
42
43
42
42
43
42
42
42
42
42
42
42
42
42
42
43
42
43
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
41
5
42
5
42
41
42
43
42
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
To J5800 MAMBA/MESA B2B
X2SON6
X2SON6
5%
25V
C0G-CERM
01005
5%
NP0-C0G-CERM
25V
5%
01005
5%
NP0-C0G-CERM
1/32W
MF
MF
1/32W
ROOM=B2B_MAMBA_MESA
25V
5%
01005
NP0-C0G-CERM
25V
5%
01005
25V
5%
1/32W
1%
01005
1/32W
1%
01005
C0G-CERM
10V
01005
5%
10V
5%
25V
NP0-C0G-CERM
01005
C0G-CERM
01005
C0G-CERM
01005
0201
6.3V
X5R-CERM
20%
1/32W
0%
MF
20%
6.3V
X5R-CERM
C0G-CERM
10V
20%
01005
6.3V
0201
6.3V
20%
0201
20%
X5R-CERM
10V
20%
X5R-CERM
0201
43
43
43
43
5
43
43
43
43
43
43
42
42
43
43
43
43
5
43
43
20
43
43
43
43
5
43
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
43
20
43
43
42
18
50
41
36
28
22
20
43
42
18
43
42
43
42
43
43
43
43
43
43
5
43
20
41
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
S
VCC
Y0
Y1
S
VCC
Y0
Y1
EN
EPAD
GND
VOUT
#29546629:Ground INA
10.0.0
59 OF 80
051-02159
1
1
1
A
1
6
3
4
OV_VMON_INA
PP_HYDRA_ACC1
PP3V0_S2
PP_VAR_USB_RVP
PP_VDD_MAIN
PP_HYDRA_ACC1_R
SYNC_MASTER=sync
MF
01005
1/20W
1%
16V
01005
0201
25V
20%
MF
0%
ROOM=OV_CUTOFF
47
50
48
47
46
33
20
5
47
46
24
50
48
47
45
42
41
40
39
38
37
32
28
25
24
22
20
19
5
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
INB
GND
OUTB
OUTA
VDD
10.0.0
61 OF 80
051-02159
A1
B1
1
1
1
1
1
A2
B2
ACC_BUCK_FB
PP_VDD_MAIN
PP1V8_S2
PP_VDD_MAIN_ACC_BUCK_VIN
ACC_BUCK_TO_PMU_AMUX
PP_ACC_VAR
I2C0_AP_SCL
I2C0_AP_SDA
SYNC_MASTER=sync
0201
20%
X5R-CERM
6.3V
20%
0402-0.1MM-1
5%
01005
6.3V
X5R-CERM
01005
10V
C0G-CERM
01005
0.47UH-20%-2.52A-0.08OHM
21
11
41
21
11
48
47
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
50
48
47
46
43
41
36
25
23
21
18
15
13
11
5
21
47
20
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
FB
SW
GND
SDA
SCL
GND
VOUT
ON
#30199192: R6210 change to 0201 to prevent Dendrite
10.0.0
62 OF 80
051-02159
1
1
1
C1
E1
E3
C4
E4
A1
D1
A3
D3
D2
C3
C2
B2
B4
1
1
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
XRES
VDDD
VCCD
VCONN2
VCONN1
GPIO_B2
I2C_0_SCL
I2C_0_SDA
SWD_IO
SWD_CLK
VSS
RD1
CC2
CC1
#29289485: Add PP to HYDRA_TO_NUB_DOCK_CONNECT
MIKEYBUS
BB USB
D20x Stiching AC Cap:
AP USBx7
VOLTAGE=4.3V
63 OF 80
051-02159
1
1
1
H4
D4
B3
B4
B1
A1
F2
E2
D1
E4
G5
G4
H3
G6
F1
E1
F7
F6
H2
G2
H6
G7
E3
F4
C3
G1
A4
C2
D2
G3
A2
B2
F5
F3
E5
D5
1
1
1
1
1
1
1
1
HYDRA_CC1
CCG2_TO_HYDRA_CC
HYDRA_TO_PMU_USB_BRICK_ID_R
90_USB_BB_DATA_P
PP3V0_S2
PP1V8_S2
10V
01005
C0G-CERM
C0G-CERM
5%
01005
10V
C0G-CERM
01005
01005
C0G-CERM
10V
01005
5%
6.3V
0201-1
6.3V
01005
0201-1
X5R
6.3V
10%
GND_VOID=TRUE
0201
7
21
10%
01005
1%
1/32W
01005
MF
5
48
5
48
5
48
5
24
5
11
11
01005
5%
C0G-CERM
10V
5%
01005
C0G-CERM
01005
C0G-CERM
5%
50
48
46
44
33
20
5
50
48
46
43
41
36
25
23
21
18
15
13
11
5
46
44
24
48
44
48
45
20
50
48
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
ACC_PWR
DVSS1
VDD3V0
UART1_TX
UART1_RX
ACC2
POW_GATE_EN*
CC0
DIG_DP
DIG_DN
USB1_DP
BRICK_ID
USB1_DN
USB0_DN
USB0_DP
UART0_RX
UART0_TX
UART2_TX
UART2_RX
JTAG_CLK
JTAG_DIO
EXT_SW_EN
FORCE_DFU
DOCK_CONNECT
CC1
DVSS
P_IN
ACC1
ACC1
ACC1
ACC1
ACC1
ACC2
ACC2
ACC2
DN1
DP1
DN2
DP2
#30797674: Update C6496/C6494 per EMC/Desense feedback
#29332151: No-stuff C6480 and C6482
ARC
ANTENNA
MICS
SOUTH SPEAKER
25V
150OHM-25%-200MA-0.7DCR
150OHM-25%-200MA-0.7DCR
10V
01005
10V
C0G-CERM
150OHM-25%-200MA-0.7DCR
10V
01005
C0G-CERM
ROOM=B2B_DOCK
10V
01005
ROOM=B2B_DOCK
ROOM=B2B_DOCK
10%
X5R
25V
10%
25V
5%
01005
25V
0201
25V
10%
X5R
0201
25V
X5R
0201
01005
1/32W
MF
01005
1/32W
01005
1%
MF
1/32W
01005
5%
25V
COG
0.00
MF
01005
0%
1/32W
0%
MF
36
13
01005
5%
220PF
01005
10V
C0G-CERM
16V
5%
01005
1/32W
0%
1/32W
01005
MF
0%
1/32W
MF
0%
1/32W
MF
25V
5%
01005
22-OHM-25%-1800MA
01005
25V
5%
01005
NP0-C0G-CERM
NP0-C0G-CERM
5%
25V
37
36
39
37
36
ROOM=B2B_DOCK
01005
25V
01005
ROOM=B2B_DOCK
ROOM=B2B_DOCK
5%
NP0-C0G-CERM
25V
NP0-C0G-CERM
01005
ROOM=B2B_DOCK
25V
5%
NP0-C0G-CERM
5%
01005
NP0-C0G
16V
5%
01005
10V
C0G-CERM
01005
10V
01005
150OHM-25%-200MA-0.7DCR
5%
10V
ROOM=B2B_DOCK
10V
5%
01005
16V
48
48
48
47
5
48
50
48
48
47
5
47
5
48
5
48
5
48
39
48
50
50
50
47
46
44
33
20
5
48
48
48
47
50
50
48
48
48
48
48
36
36
50
47
46
45
43
41
36
25
23
21
18
15
13
11
5
48
35
48
48
47
35
42
41
11
42
41
11
48
35
48
37
50
39
48
39
48
48
34
11
34
11
37
48
39
48
48
36
48
48
48
48
39
48
48
48
5
36
35
48
48
48
48
48
48
37
48
48
48
48
48
48
48
5
50
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
48
5
47
5
39
48
48
37
24
5
48
35
47
44
48
5
48
37
48
37
48
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
10.0.0
65 OF 80
051-02159
SYNC_MASTER=sync
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
10.0.0
80 OF 80
051-02159
PP1V8_S2
PP_VDD_BOOST
90_USB_BB_DATA_P
NFC_SWP
90_USB_BB_DATA_N
AP_TO_BB_MESA_ON
AP_TO_BB_COREDUMP
PP_VDD_MAIN
50_UAT_TRX_LB_MCW
SWD_AOP_TO_MANY_SWCLK
DISPLAY_TO_MANY_BSYNC
LAT_TUNER_RFFE1_DATA
UART_BB_TO_AOP_RXD
I2S_BB_TO_AP_DIN
I2S_BB_TO_AP_LRCLK
I2S_BB_TO_AP_BCLK
BB_TO_STROBE_DRIVER_GSM_BURST_IND
UART_BB_TO_WLAN_COEX
BB_TO_NFC_CLK
AP_TO_WLAN_DEVICE_WAKE
UART_AP_TO_BT_RTS_L
UART_AP_TO_BT_TXD
UART_BT_TO_AP_CTS_L
UART_BT_TO_AP_RXD
BT_TO_PMU_HOST_WAKE
50_LAT_WLAN_NORTH
50_LAT_WLAN_SOUTH
50_UAT_WLAN_5G_EAST
50_LAT_WLAN_MLC
50_UAT_WLAN_2G_EAST
UART_WLAN_TO_BB_COEX
AOP_TO_WLAN_CONTEXT_A
PP_VDD_MAIN
90_PCIE_AP_TO_WLAN_REFCLK_P
UART_BB_TO_WLAN_COEX
90_PCIE_AP_TO_WLAN_REFCLK_N
90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_WLAN_TO_AP_RXD_N
SYNC_DATE=07/18/2016
SUBDESIGN_SUFFIX=W
SUBDESIGN_SUFFIX=EF
I6
SUBDESIGN_SUFFIX=E
I5
SUBDESIGN_SUFFIX=S
I4
13
80
78
77
59
52
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
73
43
41
36
28
22
20
73
47
73
52
50
59
8
73
47
59
12
59
12
59
12
80
73
52
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
76
67
50
58
17
13
5
56
42
29
22
21
13
78
60
50
48
59
13
59
11
59
11
59
11
59
41
32
80
73
50
56
52
50
59
12
58
8
78
48
52
12
52
12
80
78
77
59
52
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
80
73
52
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
56
52
50
52
21
56
52
50
52
12
5
52
12
52
21
52
12
52
12
74
8
77
50
5
77
50
5
76
68
50
73
52
50
76
68
50
76
71
50
76
68
50
76
68
50
76
68
50
76
67
50
76
67
50
76
68
50
78
60
50
48
56
12
56
21
74
8
58
8
59
13
59
11
73
21
80
73
50
59
8
56
52
50
58
8
58
8
76
65
50
76
69
50
76
69
50
76
69
50
76
69
50
68
50
76
68
50
76
67
50
76
70
50
73
12
78
48
78
48
78
48
80
78
77
59
52
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
78
60
50
48
77
50
5
77
50
5
77
48
47
46
44
33
20
5
76
70
50
76
69
50
76
69
50
76
69
50
76
69
50
76
65
50
76
71
50
59
12
59
21
78
60
50
48
80
78
77
59
52
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
76
71
50
76
71
50
80
78
77
59
52
50
48
47
46
45
43
41
36
25
23
21
18
15
13
11
5
80
12
80
12
80
12
80
12
80
12
80
12
80
21
81
76
81
76
81
76
81
76
81
76
80
73
50
80
13
80
73
52
50
48
47
45
44
42
41
40
39
38
37
32
28
25
24
22
20
19
5
80
8
80
73
50
80
8
80
8
80
8
80
8
80
8
80
8
80
8
80
21
80
13
80
21
80
21
80
12
80
12
80
12
5
80
12
80
12
80
21
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
WLAN_TIME_SYNC
UART_AP_TO_WLAN_TXD
UART_WLAN_TO_AP_CTS_L
UART_WLAN_TO_AP_RXD
AP_TO_BT_WAKE
AP_TO_WLAN_DEV_WAKE
UART_AP_TO_BT_RTS_L
UART_AP_TO_BT_TXD
UART_BT_TO_AP_CTS_L
UART_BT_TO_AP_RXD
BT_TO_PMU_HOST_WAKE
PMU_TO_WLAN_REG_ON
50_LAT_WLAN_SOUTH
50_LAT_WLAN_MLC
50_UAT_WLAN_2G_EAST
PMU_TO_BT_REG_ON
UART_WLAN_TO_BB_COEX
90_PCIE_AP_TO_WLAN_TX_P
PCIE_AP_BI_WLAN_CLKREQ_L
AOP_TO_WLAN_CONTEXT_B
AOP_TO_WLAN_CONTEXT_A
PCIE_WLAN_TO_PMU_WAKE
PCIE_AP_TO_WLAN_PERST_L
90_PCIE_WLAN_TO_AP_RX_N
90_PCIE_WLAN_TO_AP_RX_P
90_PCIE_AP_TO_WLAN_TX_N
PP_VDD_MAIN
90_PCIE_AP_TO_WLAN_REFCLK_N
90_PCIE_AP_TO_WLAN_REFCLK_P
UART_BB_TO_WLAN_COEX
50_LHB_LAT1
50_DSM_HB_IN_TRX_UHB
50_LMHGW_UAT1
50_LAT_DRX_LB_MCS
50_LAT_DRX_MLB_MB_HB_MCS
50_UAT_TRX_MLB_MB_HB_MCS
PP3V0_TRISTAR_ARC_PROX
VDD_TUNER_RFFE_VIO_1V8
UAT_TUNER_RFFE4_CLK
UAT_TUNER_RFFE4_DATA
LAT_TUNER_RFFE1_CLK
LAT_TUNER_RFFE1_DATA
BB_TO_LAT_GPO1
BB_TO_LAT_GPO2
50_UAT_TRX_LB_MCS
50_UAT_TRX_UHB_MCS
50_LAT_DRX_LB_MCW
50_UAT_TRX_UHB_MCW
50_UAT_TRX_MLB_MB_HB_MCW
50_UAT_TRX_LB_MCW
50_LAT_DRX_MLB_MB_HB_MCW
50_LAT_WLAN_NORTH
50_UAT_WLAN_2G_EAST
BB_TO_LAT_GPO3
50_UAT_WLAN_2G_WEST
AP_TO_BB_MESA_ON_L
50_UAT_TRX_LB_MCS
50_UAT_TRX_MLB_MB_HB_MCS
PCIE0_BB_TO_AP_TX_P
PCIE0_AP_TO_BB_RX_N
PCIE0_AP_TO_BB_REFCLK_N
LAT_TUNER_RFFE1_CLK
LAT_TUNER_RFFE1_DATA
UAT_TUNER_RFFE4_DATA
UAT_TUNER_RFFE4_CLK
UART_BB_TO_AOP_RXD
I2S_BB_TO_AP_LRCLK
I2S_BB_TO_AP_DIN
I2S_BB_TO_AP_BCLK
BB_TO_AP_GSM_TXBURST
PCIE0_AP_TO_BB_REFCLK_P
PCIE0_AP_TO_BB_RX_P
90_USB_BB_P
NFC_TO_PMU_HOST_WAKE
AP_TO_NFC_DEV_WAKE
NFC_SWP1
PP1V8_SDRAM
PP_VDD_MAIN
BB_TO_NFC_CLK
PMU_TO_NFC_EN
NFC_TO_BB_CLK_REQ
AP_TO_NFC_FW_DWLD
MAY 15, 2017
AP_TO_NFC_FW_DWLD_REQ
NFC_SWP
0008927012
10
ENGINEERING RELEASED
10.0.0
PMU_TO_NFC_EN
AP_TO_NFC_DEV_WAKE
NFC_TO_PMU_HOST_WAKE
BB_TO_NFC_CLK
NFC_TO_BB_CLK_REQ
UART_AP_TO_NFC_TXD
UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_RTS_L
UART_NFC_TO_AP_CTS_L
131S00016
D201
1
C7514_S
T7500_S
MURATA, BALUN, 11T
157S00023
1
D21_JPN
680PF, 0201, 2%, 25V
131S00033
C7513_S
1
D21_JPN
157S00023
MURATA, BALUN, 11T
T7500_S
D21_ROW
1
C7514_S
D211
270PF, 0201, 2%, 25V
1
131S00081
131S00033
C7510_S
D21_JPN
680PF, 0201, 2%, 25V
1
C7518_S
D21_JPN
150PF, 0201, 2%, 50V
1
131S00019
TDK, BALUN, 11T
157S00022
D20_JPN
1
T7500_S
131S00025
1000PF, 0201, 2%, 25V
D20_JPN
1
C7513_S
39PF, 0201, 2%, 50V
D21_ROW
C7512_S
1
131S00138
39PF, 0201, 2%, 50V
C7512_S
D21_JPN
131S00138
1
270PF, 0201, 2%, 25V
C7514_S
D21_JPN
131S00081
1
C7515_S
D21_JPN
1000PF, 0201, 2%, 25V
131S00025
1
680PF, 0201, 2%, 25V
C7516_S
D21_JPN
131S00033
1
D21_ROW
150PF, 0201, 2%, 50V
C7518_S
131S00019
1
C7512_S
D211
1
39PF, 0201, 2%, 50V
131S00138
C7516_S
680PF, 0201, 2%, 25V
D211
1
131S00033
C7518_S
131S00019
D211
150PF, 0201, 2%, 50V
1
680PF, 0201, 2%, 25V
C7510_S
D211
1
131S00033
820PF, 0201, 2%, 25V
131S00026
D201
1
C7510_S
131S00138
39PF, 0201, 2%, 50V
1
C7512_S
157S00023
T7500_S
D211
MURATA, BALUN, 11T
1
680PF, 0201, 2%, 25V
C7513_S
D211
1
131S00033
C7515_S
D211
1000PF, 0201, 2%, 25V
1
131S00025
D21_ROW
680PF, 0201, 2%, 25V
C7513_S
1
131S00033
680PF, 0201, 2%, 25V
131S00033
D21_ROW
C7510_S
1
C7515_S
131S00025
1000PF, 0201, 2%, 25V
D21_ROW
1
131S00033
680PF, 0201, 2%, 25V
1
D21_ROW
C7516_S
270PF, 0201, 2%, 25V
131S00081
D21_ROW
C7514_S
1
131S0882
390PF, 0201, 2%, 25V
D20_JPN
1
C7514_S
131S00025
D201
1
1000PF, 0201, 2%, 25V
C7515_S
131S0825
560PF, 0201, 2%, 25V
D201
1
C7516_S
131S0883
220PF, 0201, 2%, 50V
D201
1
C7518_S
131S00026
820PF, 0201, 2%, 25V
D201
1
C7513_S
157S00022
TDK, BALUN, 11T
D201
1
T7500_S
131S00026
820PF, 0201, 2%, 25V
D20_JPN
1
C7515_S
131S00025
1000PF, 0201, 2%, 25V
D20_JPN
1
C7510_S
680PF, 0201, 2%, 25V
D20_JPN
1
131S00033
C7516_S
131S0883
220PF, 0201, 2%, 50V
D20_JPN
1
C7518_S
C7512_S
1
39PF, 0201, 2%, 50V
131S00138
D20_ROW
C7514_S
1
470PF, 0201, 2%, 25V
131S00016
D20_ROW
C7515_S
1000PF, 0201, 2%, 25V
1
131S00025
D20_ROW
C7518_S
1
220PF, 0201, 2%, 50V
131S0883
D20_ROW
C7516_S
1
560PF, 0201, 2%, 25V
131S0825
D20_ROW
C7510_S
1
820PF, 0201, 2%, 25V
131S00026
D20_ROW
C7513_S
1
820PF, 0201, 2%, 25V
131S00026
D20_ROW
T7500_S
1
TDK, BALUN, 11T
157S00022
D20_ROW
C7500_S,C7502_S, C7505_S
SOFT_CAP
138S00159
CRITICAL
CAP,SOFT TERM,2.2UF,6.3V,0201
3
TYPICAL_CAP
CRITICAL
C7500_S,C7502_S,C7505_S
138S0831
3
CAP,TYPICAL,2.2UF,6.3V,0201
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
52
50
QTY
DESCRIPTION
PART#
CRITICAL
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
REV
DESCRIPTION OF REVISION
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
APPD
1
1
2
4
5
6
7
B
D
6
5
4
3
C
A
A
D
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
051-02159
52 OF 81
10.0.0
C7507_S
C7513_S
L7501_S
C7517_S
TP7506_S
C7523_S
VDD_NFC_5V_S
C7520_S
L7502_S
NFC_DCDC_S
PP7513_S
TP7500_S
PP7512_S
PP7511_S
Q7501_S
1
MF
201
1%
1K
NFC
1
SM
OMIT
P2MM-NSM
1
SM
OMIT
P2MM-NSM
1
SM
OMIT
P2MM-NSM
1
SM
OMIT
P2MM-NSM
1
SM
OMIT
P2MM-NSM
1
SM
OMIT
P2MM-NSM
1
SM
OMIT
P2MM-NSM
1
20%
6.3V
2.2UF
0201
1
0201
20%
6.3V
2.2UF
50
1
0201
2%
25V
NFC
820PF
1
0201
2%
25V
820PF
NFC
TP-P55
OMIT
NFC
1
NFC
6.3V
20%
X5R
01005-1
1
01005
20%
6.3V
NFC
0.1UF
51
50
52
51
50
52
51
50
52
51
50
52
51
50
52
51
50
51
50
51
50
51
50
52
51
50
1
0201
20%
6.3V
OMIT_TABLE
NFC
2.2UF
1
MF
01005
0%
NFC
0.00
1
0201
20%
6.3V
OMIT_TABLE
NFC
2.2UF
1
NFC
106NH-5%-0.85A-0.144OHM
51
50
52
51
50
52
51
50
52
51
50
52
51
50
52
51
50
52
51
50
52
51
50
52
51
50
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
NFC_GPIO6
XTAL2
ESE_VSS
PVSS
TVSS
DVSS
AVSS
AVSS
VDD
SIM_VCC2
GPIOVDD
SVDD
AVDD
TVDD
VUP
PVDD
SIM_PMU_VCC_2
VBAT
ESE_GPIO
ESE_DWPS_DBG
ESE_DWPM_DBG
RX-
RX+
SIM_SWIO_2
NFC_GPIO4
TX2
TX1
VMID
WKUP_REQ
NFC_GPIO1
NFC_GPIO0
NFC_GPIO3
NFC_GPIO2
NFC_GPIO5
IRQ
DWL
UART_TX
UART_RX
VEN
UART_RTS
UART_CTS
IC5
IC1
IC3
IC2
IC6
IC7
IC0
NFC_CLK_XTAL1
IC14
IC13
IC10
CLK_REQ
IC11
PORT2
PORT3
GND
PVIN
VOUT
VOUT
MODE0
MODE1
PGND
S
S
S
S
REV
DESCRIPTION OF REVISION
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
APPD
1
1
2
4
5
6
7
B
D
6
5
4
3
C
A
A
D
SYNC
CONTENTS
CSA
PAGE
BOM OPTION
REFERENCE DESIGNATOR(S)
PART NUMBER
ALTERNATE FOR
PART NUMBER
AUDIO
AOP
SWD/USB
TUNER/DOCK
RF SIGNALS
STOCKHOLM
PCIE
AP_TO_BB_COREDUMP
AP_TO_BB_MESA_ON
AP_TO_BB_IPC_GPIO1
90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N
90_PCIE_AP_TO_BB_TXD_P
90_PCIE_BB_TO_AP_RXD_N
90_PCIE_BB_TO_AP_RXD_P
UAT_TUNER_RFFE_CLK
2
4
5
6
7
8
B
D
8
7
6
5
4
3
C
B
A
C
A
D
2
1
3
1.20V/695MA
0.90V/128MA
1.80V/272.4MA
1.8V/60MA
3.00V/30MA
1.2V/1366MA
0.80V/2898MA
1.80V/509MA
X5R
20%
4V
X5R
20%
4V
X5R
20%
4V
0402-0.1MM
20%
4V
X5R
20%
4V
0402-0.1MM
20%
4V
X5R
20%
4V
X5R
20%
4V
0402-0.1MM
20%
4V
0201
X5R-CERM
6.3V
0201
6.3V
20%
0201
6.3V
X5R-CERM
0402-0.1MM
20%
CERM
10V
20%
X5R-CERM
10V
20%
X5R-CERM
10V
20%
X5R-CERM
X5R-CERM
20%
10V
0402-0.1MM-1
10UF
10V
20%
X5R-CERM
0402-0.1MM
20%
6.3
X5R
20%
6.3
0402-0.1MM
20%
6.3
0402-0.1MM
6.3
20%
1/32W
01005
0%
3
2
16V
01005
8
5
5
20
16
15
13
12
11
8
5
4
21
10
8
7
6
5
4
3
8
5
21
5
5
6.3V
402
X5R-CERM1
6.3V
402
X5R-CERM1
10
3
2
3
3
3
4
3
5
3
4
3
5
ROOM=PMU
SHORT-10L-0.1MM-SM
ROOM=PMU
ROOM=PMU
SHORT-10L-0.1MM-SM
RADIO_PMIC
2016
ROOM=PMU
ROOM=PMU
SHORT-10L-0.1MM-SM
3
2
21
3
2
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
LREG
VREG_L2
VREG_L5
VREG_L6
VREG_L10
VREG_L13
VREG_L12
VDD_L4
VDD_L1_2
VDD_L1_2
VIN_VPH1
VIN_VPH2
VDD_L5_6
VDD_L7
SYM 6 OF 6
GND_S1
VDD_S1
VDD_S1
VDD_S1
GND_S1
GND_S2
VDD_S2
VDD_S3
GND_S3
GND_S3
VDD_S3
GND_S4
VDD_S4
GND_S5
GND_S5
VDD_S5
VDD_S5
VREG_S1
VSW_S1
VREG_S2
VSW_S2
VSW_S3
VSW_S3
VREG_S3
VSW_S2
VREG_S4
VSW_S4
VREG_S5
VSW_S5
MAV17.0
MAV17.1
MAV17.2
2
ROW
ROW
4
51.1K
180K
9
A
SKU
28K
CARRIER/DEV5
66.5K
R408
16.5K
7.87K
51.1K
51.1K
R431
10K
SPARE
105K
ROW
3
EVT
51.1K
3RD TYPE
SPARE
51.1K
0.55V-0.65V
PROTO2.5/DEV2
51.1K
51.1K
180K
422K
0.10V
51.1K
1.15V-1.25V
1.35V-1.45V
6
5
1
6
51.1K
8
44.2K
66.5K
16.5K
7.87K
1.35V-1.45V
51.1K
1.55V-1.65V
1.35V-1.45V
7
MLB
JPN
JPN
ROW
9
51.1K
28K
0.55V-0.65V
MAV17.9
JPN
MAV17.6
MAV17.5
MAV17.4
83
92
91
81
46
45
37
26
71
67
70
51
62
61
47
25
40
38
5
6
60
17
7
15
35
50
39
48
18
16
8
28
1
2
2
1
2
2
87
56
55
89
106
79
69
59
1
68
X5R-CERM
6.3V
01005
X5R-CERM
20%
6.3V
01005
RADIO_PMIC
0.00
1/32W
RADIO_PMIC
01005
CER-X6S
16V
0402
RADIO_PMIC
X5R-CERM
RADIO_PMIC
6.3V
BGA
CERM
5%
1/32W
MF
0%
01005
ROOM=PMU
SHORT-10L-0.1MM-SM
SHORT-10L-0.1MM-SM
ROOM=PMU
1/32W
0%
MF
RADIO_PMIC
RADIO_PMIC
MF
1/32W
5%
1/32W
MF
RADIO_PMIC
01005
MF
RADIO_PMIC
1/32W
RADIO_PMIC
SHORT-10L-0.1MM-SM
1%
01005
MF
RADIO_PMIC
01005
RADIO_PMIC
0%
MF
0%
MF
RADIO_PMIC
01005
RADIO_PMIC
1%
RADIO_PMIC
1%
1/32W
1/32W
MF
1%
01005
5%
1/32W
1/32W
1%
5%
1/32W
1000PF
38.4MHZ-10PPM-7PF
1.6X1.2-SM
RADIO_PMIC
MF
1/32W
1%
MF
1/32W
6.3
0402-0.1MM
ROW
1
JPN
CRITICAL
1
AP_TO_BBPMU_RADIO_ON_L
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GPIO
OPT_2
GPIO_07
GPIO_02
GPIO_01
GPIO_04
GPIO_03
GPIO_05
GPIO_06
MISC
RESIN*
BAT_ID_THERM
PA_THERM3
PA_THERM2
SYM 1 OF 6
XTAL_OUT
GND_XO_CLK
GND_XOADC
XTAL_IN
VDD_XO_RF
VREG_RF
LN_BB_CLK
RF_CLK1
RF_CLK2
GND_RF_CLK
GND_XO
VREG_XO
SLEEP_CLK
SYM 2 OF 6
GND
GND
GND
GND
GND
GND
GND
1
2
2
2
2
1
2
1
2
1
2
1
2
1
2
AA20
AA18
AA14
T14
T13
R6
R5
P7
N19
M20
M17
L17
L16
L8
K16
K8
K1
J21
J15
J7
H20
H14
H10
H9
G21
G8
F19
F1
E21
E20
E15
D4
C21
C14
C12
C9
B19
A16
A12
A7
138S0831
138S00159
6.3V
0201-1
10%
6.3V
0201-1
10%
6.3V
X5R-CERM
0201-1
6.3V
0201-1
10%
6.3V
0201-1
X5R-CERM
6.3V
0201-1
X5R-CERM
6.3V
0201-1
10%
6.3V
0201-1
X5R-CERM
6.3V
X5R-CERM
6.3V
0201-1
X5R-CERM
6.3V
0201-1
10%
6.3V
X5R-CERM
6.3V
20%
6.3V
0201
6.3V
X5R-CERM
0201
01005
6.3V
X5R-CERM
20%
6.3V
X5R-CERM
SHORT-10L-0.1MM-SM
ROOM=PMU
6.3V
01005-1
SHORT-10L-0.1MM-SM
ROOM=PMU
01005
6.3V
20%
6.3V
X5R
01005-1
6.3V
X5R
01005-1
6.3V
X5R
01005-1
BGA
6.3V
20%
01005
6.3V
X5R-CERM
01005
6.3V
X5R-CERM
01005
6.3V
20%
01005
6.3V
X5R-CERM
01005
6.3V
X5R-CERM
01005
6.3V
X5R-CERM
01005
6.3V
20%
X5R-CERM
6.3V
X5R-CERM
01005
6.3V
20%
X5R-CERM
X5R-CERM
01005
6.3V
X5R-CERM
6.3V
X5R-CERM
6.3V
20%
X5R-CERM
6.3V
20%
X5R-CERM
01005
6.3V
X5R-CERM
01005
6.3V
X5R-CERM
01005
6.3V
X5R-CERM
01005
6.3V
X5R-CERM
01005
6.3V
20%
01005
6.3V
X5R-CERM
X5R-CERM
6.3V
6.3V
X5R
20%
6.3V
X5R
01005-1
BGA
0.22UF
X5R
6.3V
01005-1
6.3V
X5R
01005-1
X5R
01005-1
6.3V
X5R
01005-1
6.3V
X5R
01005-1
6.3V
X5R
01005-1
6.3V
X5R
01005-1
6.3V
X5R
01005-1
6.3V
X5R
01005-1
6.3V
X5R
01005-1
BGA
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
QTY
DESCRIPTION
PART#
CRITICAL
PWM2
VDD_DDR_CORE_1P8
VDD_DDR_CORE_1P8
VDD_PCIE_1P8
VDD_P1
VDD_P3
VDD_PCIE_0P9
VDD_P1
VDD_DDR_CORE_1P2
VDD_DDR_CORE_1P2
VDD_USB_HS_3P1
VDD_DDR_CORE_1P8
VDD_USB_HS_1P8
VDD_USB_SS_1P8
VDD_DDR_CORE_1P8
VDD_DDR_CORE_1P2
VDD_DDR_CORE_1P2
VREF_SDC
VREF_UIM
VDD_QLINK_IO_0P9
VDD_PLL
VDD_QFPROM_PRG
VDD_ALWAYS_ON
VDD_P1
VDD_P1
VDD_P1
VDD_P1
VDD_P2
VDD_P3
VDD_P3
VDD_P3
VDD_P1
VDD_P1
VDD_P4
VDD_P5
VDD_P3
VDD_P3
VDD_P7
VDD_P7
VDD_PCIE_0P9
VDD_USB_HS_0P9
VDD_USB_SS_0P9
VDD_USB_SS_0P9
SYM 7 OF 8
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MODEM
VDD_MODEM
VDD_MODEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
SYM 6 OF 8
BDM_ZQ
EBI1_CAL
VREF_DQ1
VREF_DQ0
SYM 1 OF 8
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_TX_P
PCIE_TX_M
PCIE_RX_P
PCIE_RX_M
PCIE_REXT
USB_HS_DM
NC
USB_SS_TX_P
USB_SS_TX_M
USB_SS_RX_P
USB_SS_RX_M
USB_SS_REXT
USB_HS_REXT
SYM 3 OF 8
SDC1_CMD
SDC1_DATA_0
SDC1_DATA_2
SDC1_DATA_3
SPMI_CLK
SPMI_DATA
SDC1_DATA_1
RESOUT*
PS_HOLD
CXO_EN
CXO
SRST*
RESIN*
SLEEP_CLK
MODE_0
MODE_1
TCK
TRST*
EUREKA CONFIG
I2C MOVE PER EUREKA
PER EUREKA
PER RFSW. MOVED TO PIN50
MPM
NOR SPI STATUS - RF DEV ONLY
2
7
2
2
4
21
21
21
21
22
2
22
2
22
2
2
22
2
RADIO_BB
1%
MF
X5R
0201
10V
20%
MF
1%
01005
RADIO_BB
WLCSP
MF
1/32W
01005
1/32W
01005
8
MF
0%
01005
RADIO_WTR
RADIO_WTR
1/32W
MF
01005
0%
7
2
21
7
2
22
2
22
2
21
7
2
2
21
7
2
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
SYM 5 OF 8
GPIO_12
GPIO_46
GPIO_59
GPIO_60
GPIO_54
GPIO_21
GPIO_22
GPIO_55
GPIO_11
GPIO_10
GPIO_14
GPIO_58
GPIO_57
GPIO_56
GPIO_70
GPIO_71
GPIO_36
GPIO_79
GPIO_78
GPIO_77
GPIO_76
GPIO_69
GPIO_68
GPIO_67
GPIO_66
GPIO_53
GPIO_52
GPIO_48
GPIO_47
GPIO_45
GPIO_44
GPIO_39
GPIO_37
GPIO_35
GPIO_34
GPIO_27
GPIO_26
GPIO_20
GPIO_19
GPIO_17
GPIO_16
GPIO_8
GPIO_7
ANALOG_RF
NC
NC
NC
NC
NC
QLINK_DL0_M
QLINK_CLK_P
QLINK_CLK_M
QLINK_DL1_P
QLINK_UL0_P
QLINK_UL0_M
QLINK_DL1_M
QLINK_DL2_P
VSS
SDA
SCL
SHARE WITH PIN 233
2
2
2
2
LAT_TUNER_RFFE1_CLK
0%
MF
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
NOSTUFF
01005
6.3V
20%
NOSTUFF
01005
6.3V
20%
01005
6.3V
20%
NOSTUFF
6.3V
X5R-CERM1
402
01005
6.3V
20%
01005
6.3V
20%
01005
MF
1/32W
6.3V
402
X5R-CERM1
01005
0%
MF
1/32W
402
X5R-CERM1
01005
6.3V
20%
01005
6.3V
20%
NOSTUFF
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
01005
6.3V
20%
1/32W
0%
01005
MF
1/32W
0%
MF
1/32W
0%
6.3V
20%
01005
6.3V
20%
2
7
2
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VDD_1P2_ANA
VDD_1P2_STG
VDD_1P0_TX0
VDD_1P2_TX0
VDD_1P8_TX0
VDD_1P8_ANA0
VDD_1P0_TX1
VDD_1P8_TX1
VDD_1P8_ANA1
VDD_1P0_TX
DNC
VDD_1P0_XO
VDD_1P0_QLINK
VDD_1P0_GNSS
VDD_1P0_RX0
DNC
VDD_1P0_RX2
VDD_1P0_RX
VDD_1P2_ANA4
VDD_1P2_ANA3
VDD_1P0_RX1
DNC
DNC
VDD_1P2_RX0
VDD_1P2_ANA1
VDD_1P8_FBRX
VDD_1P8_ANA2
GND
GND
GND
DNC
W_GRFC_9
W_GRFC_8
W_GRFC_7
W_GRFC_1
W_GRFC_3
W_GRFC_2
W_GRFC_0
STRIPLINE
ROW = STUFF
JPN = STUFF
QTY
DESCRIPTION
PART#
CRITICAL
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
TX_FBRX-
DNC
DNC
DNC
DNC
DNC
DRX_MB_B
DRX_UHB_LTEU_A
DNC
DNC
DNC
DRX_LB
DNC
DRX_UHB_LTEU_B
DRX_MB_A
DRX_LHB
DRX_HB
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRX_LB
PRX_UHB_LTEU_A
GND132
TX_FBRX+
PRX_HB
PRX_LHB
GND
GND
GND
PRX_MB_A
PRX_UHB_LTEU_B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TX_CH1_MB2
TX_CH1_LMB1
TX_CH1_UHB
TX_CH1_MB
TX_CH1_HB1
TX_CH0_LMB
TX_CH0_LB2
TX_CH0_MB2
TX_CH0_MB1
TX_CH0_HB2
DNC
DNC
DNC
VREF_DAC
DNC
DNC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GND
VCC_PA_GSM1
VCC_PA_GSM0
VDD_1P8
VBAT_SW
VBAT
SDATA
RADIO_LB_PAD
0%
MF
25V
C0G-CERM
LGA
01005-1
10%
CERM
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
QTY
DESCRIPTION
PART#
CRITICAL
THRM_PAD
THRM_PAD
THRM_PAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
LB_ANT
TX_LB_IN
VCC1
VBATT
SCLK_RX
SDATA_RX
VCC2
SCLK_TX
VIO_TX
VIO_RX
99
95
94
85
84
75
74
65
64
55
54
45
44
26
22
9
7
6
28
40
17
18
41
20
14
8
30
24
29
36
34
32
62
1
2
1
2
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
2
2
1
2
1
2
2
1
152S2000
2.0NH UHQ, HB ANT MATCH
R1210_E
ROW
1
CRITICAL
131S0329
ROW
C1209_E
1
0.4PF, HB ANT MATCH
CRITICAL
CRITICAL
1
JPN
1.8NH UHQ, HB ANT MATCH
152S2042
R1210_E
JPN
R1209_E
152S2023
3.2NH UHQ, 2G HB PAD MATCH
1
131S0425
JPN
1
CRITICAL
C1209_E
0.5PF, HB ANT MATCH
JPN
R1211_E
1NH UHQ, 2G HB PAD MATCH
152S00153
1
CRITICAL
HB-PAD-AFEM-8072
25V
C0G-CERM
25V
C0G
+/-0.05PF
01005
MF
0%
1/32W
1/20W
5%
16V
5%
NP0-C0G
01005
0201
RADIO_HB_PAD
1%
RADIO_HB_PAD
CERM
5%
16V
NOSTUFF
RADIO_HB_PAD
MF
1/32W
10%
10V
01005
1/32W
1%
NOSTUFF
C0G-CERM
RADIO_HB_PAD
16V
NOSTUFF
01005
01005
NP0-C0G
16V
RADIO_HB_PAD
10%
RADIO_HB_PAD
X5R-CERM
RADIO_HB_PAD
0%
MF
01005
C0G-CERM
+/-0.05PF
RADIO_HB_PAD
NOSTUFF
16V
CER-X5R
16V
20%
0201
20%
X5R-CERM
6.3V
RADIO_HB_PAD
1/32W
0%
RADIO_HB_PAD
MF
01005
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
QTY
DESCRIPTION
PART#
CRITICAL
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SDATA_RX
PRX_HB1
PRX_MB2
TX_2GHB_OUT
TX_MB_IN
TX_HB_IN
SCLK_RX
VIO_TX
SDATA_TX
SCLK_TX
VBATT
VCC1
VCC2
VBIAS_LNA
ANT
JPN = STUFF
25V
COG-CERM
RADIO_UHB_PAD
16V
+/-0.1PF
NP0-C0G
0201
20%
01005
X5R
0201-1
0201
RADIO_2G_PA
1/20W
MF
0201
RADIO_2G_PA
NOSTUFF
0201
MF
20%
X5R-CERM
01005
10V
10%
NOSTUFF
1.00
1/32W
1%
MF
NOSTUFF
NOSTUFF
RADIO_UHB_PAD
CERM
16V
01005
MF
1/32W
0%
+/-0.05PF
NOSTUFF
01005
C0G-CERM
RADIO_UHB_PAD
C0G-CERM
RADIO_UHB_PAD
01005
MF
0%
RADIO_UHB_PAD
01005
5%
16V
01005
CERM
01005
NOSTUFF
5%
RADIO_UHB_PAD
5%
01005
RADIO_UHB_PAD
16V
NOSTUFF
RADIO_UHB_PAD
16V
5%
CERM
RADIO_UHB_PAD
1/20W
0201
MF
01005
1/32W
MF
0201
1/20W
RADIO_UHB_PAD
5%
CERM
01005
NOSTUFF
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GND
VCC2
VBATT
VCC1
SDATA_TX
VIO_TX
SCLK_TX
SDATA_RX
VIO_RX
SCLK_RX
ANT_UHB2
CPL_OUT3
ANT_MLB1
NC/GND
TX_MLB_IN
TX_UHB_IN
PRX_MLB1
PRX_UHB1
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GND
GND
GND
GND
GND
GND
VIO
SDATA
SCLK
DRX_LB_IN_3
DRX_LB_OUT_1
DRX_LB_IN_2
QTY
DESCRIPTION
PART#
CRITICAL
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
VIO
SCLK
SDATA
DRX_HB_IN2
DRX_UHB_IN3
DRX_HB_OUT1
DRX_HB_OUT2
RADIO_CPL2
NOSTUFF
25V
2
2
2
QTY
DESCRIPTION
PART#
CRITICAL
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VIO
RFFE_CLK
VDD
TRX_HB_IN
RF_CPL3_IN
DRX_HB_OUT
TRX_HB_UAT
TRX_HB_LAT
TRX_LB_LAT
TRX_LB_UAT
DRX_LB_OUT
TERMINATE
MAIN_OUT
IN
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
UHB
GND
LB
MLB-MB-HB
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
MLB_MB_HB
WIFI
ANT
LB
EPAD
GND
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GND
GNSS
LB
GND
GNSS
LB
RFIN
LNA_EN
GND
RFOUT
FLEX 516S1184
MLB 516S1185
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
PART NUMBER
UART
SPMI
CLK
PP35_E
PP20_E
PP23_E
PP21_E
PP18_E
PP57_E
PP54_E
PP55_E
PP56_E
PP50_E
PP52_E
PP40_E
PP24_E
PP31_E
PP29_E
PP30_E
PP28_E
PP27_E
PP26_E
PP25_E
PP34_E
PP33_E
PP2_E
10
11
12
13
11
12
13
8
8
8
8
8
8
8
8
8
8
6
6
6
6
7
6
6
7
7
20
4
6
6
22 OF 22
051-02159
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I2S_BB_TO_AP_DIN
UART_AOP_TO_BB_TXD
I2S_BB_TO_AP_BCLK
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
D21 RADIO_MLB_FF
PP1V8_S2
UAT_TUNER_RFFE_CLK
0008927012
10
ENGINEERING RELEASED
10.0.0
50_UAT_TRX_MLB_MB_HB_MCS
50_LAT_DRX_MLB_MB_HB_MCS
50_LMHGW_UAT1
50_LAT_DRX_LB_MCS
50_UAT_TRX_MLB_MB_HB_MCW
50_UAT_TRX_LB_MCW
50_LAT_WLAN_NORTH
50_UAT_TRX_UHB_MCS
50_UAT_TRX_UHB_MCW
50_UAT_WLAN_5G_EAST
50_LAT_WLAN_SOUTH
50_UAT_WLAN_2G_EAST
50_LAT_WLAN_MLC
BB_TO_LAT_GPO3
BB_TO_LAT_GPO4
BB_TO_LAT_GPO1
LAT_TUNER_RFFE1_CLK
50_DSM_HB_IN_TRX_UHB
50_LAT_DRX_LB_MCW
50
78
50
78
50
78
50
78
50
78
50
78
50
78
50
76
50
76
50
76
50
76
50
77
50
78
77
50
77
50
78
77
50
76
50
76
50
76
50
76
50
76
50
76
50
76
50
76
50
76
50
76
50
76
50
76
50
76
50
76
50
REV
DESCRIPTION OF REVISION
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
APPD
1
1
2
4
5
6
7
B
D
6
5
4
3
C
A
A
D
LB/MLB/MB/HB
QTY
DESCRIPTION
PART#
CRITICAL
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
LBP
HBP
COMMP
GND
SIG1-S
SIG6-S
SIG5-S
SIG6-N
SIG1-N
SIGNAL4-W
SIGNAL7-W
SIGNAL6-W
SIGNAL2-W
SIGNAL1-W
SIGNAL7-E
SIGNAL6-E
SIGNAL5-E
SIGNAL1-E
GND
GND
R
GND
R
GND
PINOUT IS ROTATED 180
STANDOFF
LB/MLB/GNSS/MB/HB
TUNFX_EF
FL6700_EF
C6701_EF
C7731_EF
C7730_EF
L8003_EF
C6737_EF
L6701_EF
C6755_EF
SP2T2_EF
C6750_EF
L6752_EF
L6751_EF
C6753_EF
L8007_EF
SUAT1_EF
AGND_EF
C6738_EF
C6733_EF
C6732_EF
C6731_EF
C6730_EF
C6735_EF
C6734_EF
C8001_EF
C8005_EF
L8002_EF
C8004_EF
C8003_EF
C8002_EF
L8001_EF
75
75
78
UAT_TUNER_RFFE4_CLK_FILT_EF
PP3V0_TRISTAR_UAT_TUNER_B2B_FILT_EF
75
77
UAT_TUNER_GPO1_EF
75
77
UAT_TUNER_GPO4_EF
75
78
USP2T2_RF2_EF
USP2T2_RF1_EF
UAT_TUNER_GPO_FIL3_EF
50_UAT1_FEED_EF
USPST_RF1_EF
ALT_GND_RF1_EF
ALT_GND_RF2_EF
USPST_RF2_EF
ALT_GND_RF_EF
75
77
CHASSIS_GND_EF
UAT_TUNER_GPO_FIL1_EF
UAT_TUNER_GPO_FIL2_EF
VOLTAGE=0V
3 OF 4
051-02159
L8005_EF
152S1240
1
CRITICAL
JPN
ROW
152S00749
CRITICAL
1
L8005_EF
3.6NH 03015 WW INDUCTOR
1
2
3
4
5
6
7
8
9
10
1
2
1
2
5%
01005
2
NP0-C0G
UAT
2
UP_RFFE
2
1%
1/20W
UP_RFFE
0201
2
C0G-CERM
UP_RFFE
2
1
2
03015
1
0.6PF
2
0201
CERM
25V
+/-0.05PF
1
2
0201
25V
1
2
C0G-CERM
2
3
7
1
2
3
7
1
2
0201-1
X5R-CERM
2
1
2
2%
2
2
2
1
2
MF
1/32W
2
1
2
2
0%
01005
2
0201
2%
CERM
2
UP_RFFE
01005
2
NP0-C0G
2
NP0-C0G
UAT
2
NOSTUFF
2
2
5%
NP0-C0G
01005
2
01005
NP0-C0G
2
NP0-C0G-CERM
2
0201-1
X5R-CERM
2
0201
2
C0H-CERM
2%
2
0201
2
01005
5%
2
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
QTY
DESCRIPTION
PART#
CRITICAL
CB2
RF1
RF2
CB1
NC
GND
CB2
RF1
RF2
CB1
NC
GND
USID=0X8
C6916_EF
R6913_EF
C6910_EF
GPOUAT_EF
C6912_EF
C6913_EF
PP1V8_GPOUAT_EF
PP1V8_S2
75
78
GPOLAT_RFFE1_DATA_FILT_EF
GPOUAT_RFFE4_CLK_FILT_EF
75
77
75
77
75
78
4 OF 4
051-02159
BB_TO_LAT_GPO2
BB_TO_LAT_GPO4
BB_TO_LAT_GPO3
LAT_TUNER_RFFE1_DATA
1
16V
5%
NP0-C0G-CERM
1
MF
1
0%
1/32W
1
0201
10V
20%
2
1
0201
X5R
10V
B2
A2
A1
C3
C4
C2
C1
A4
A3
A2
A1
B4
B2
A4
1
5%
01005
16V
2
1
1/32W
MF
1
1
16V
NP0-C0G-CERM
01005
1
NP0-C0G-CERM
01005
16V
5%
1
NP0-C0G-CERM
5%
2
1
1/32W
0%
01005
1
NP0-C0G-CERM
5%
16V
2
1
50
75
50
75
50
75
50
75
50
75
50
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
GPO6
GPO2
GPO1
GND
VIO
SCLK
USID1
SDATA
SDATA
SCLK
GND
GPO1
GPO2
GPO3
D21X WIFI_MLB (GUINNESS)
CLOCKS
AOP
COEX
ANTENNA
WLAN PCIE
CONTROL
UART_BT_TO_AP_RXD
UART_WLAN_TO_AP_CTS_L
UART_WLAN_TO_AP_RXD
UART_BB_TO_WLAN_COEX
AOP_TO_WLAN_CONTEXT_B
AOP_TO_WLAN_CONTEXT_A
UART_AP_TO_BT_RTS_L
UART_AP_TO_BT_TXD
UART_AP_TO_WLAN_RTS_L
UART_AP_TO_WLAN_TXD
90_PCIE_AP_TO_WLAN_REFCLK_N
90_PCIE_AP_TO_WLAN_REFCLK_P
AP_TO_BT_WAKE
PMU_TO_BT_REG_ON
PMU_TO_WLAN_REG_ON
BT_TO_PMU_HOST_WAKE
PP_VDD_MAIN
77
WIFI FRONT-END
CONTENTS
PDF PAGE
CSA PAGE
2
GUINNESS
50
81
50
81
50
81
50
81
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
80
50
REV
DESCRIPTION OF REVISION
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
APPD
1
1
2
4
5
6
7
B
D
6
5
4
3
C
A
A
D
TDO
C7600_W
R7600_W
WLAN_W
C7608_W
PP7613_W
PP7620_W
PP7621_W
PP7623_W
PP7624_W
PP7610_W
PP7614_W
PP7615_W
PP7616_W
PP7618_W
PP7619_W
PP7600_W
PP7603_W
PP7604_W
PP7605_W
PP7606_W
PP7608_W
PP7609_W
C7603_W
C7604_W
L7600_W
C7606_W
C7607_W
90_PCIE_WLAN_TO_AP_RXD_P
90_PCIE_AP_TO_WLAN_TXD_N
SR_LVX_1_W
90_PCIE_AP_TO_WLAN_TXD_N
79
80
AOP_TO_WLAN_CONTEXT_A
AOP_TO_WLAN_CONTEXT_B
UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_TXD
90_PCIE_AP_TO_WLAN_REFCLK_P
PMU_TO_WLAN_REG_ON
PMU_TO_BT_REG_ON
UART_BT_TO_AP_RXD
UART_AP_TO_BT_RTS_L
AP_TO_BT_WAKE
UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_TXD
UART_AP_TO_WLAN_RTS_L
UART_WLAN_TO_AP_RXD
UART_WLAN_TO_AP_CTS_L
BT_TO_PMU_HOST_WAKE
UART_AP_TO_WLAN_TXD
PMU_TO_BT_REG_ON
UART_WLAN_TO_BB_COEX
PMU_TO_WLAN_REG_ON
UART_BB_TO_WLAN_COEX
AP_TO_BT_WAKE
UART_BT_TO_AP_CTS_L
UART_BT_TO_AP_RXD
UART_AP_TO_BT_RTS_L
PP_VDD_MAIN
UART_AP_TO_BT_TXD
90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N
AOP_TO_WLAN_CONTEXT_A
AOP_TO_WLAN_CONTEXT_B
ALT WIFI/BT MODULE
WLAN_W
BOM_TABLE_ALTS
339S00397
SYNC_DATE=11/28/2016
6.3V
X5R
2
16V
5%
01005
NP0-C0G
2
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
79
50
79
50
80
79
50
80
79
50
80
79
50
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
5%
01005
1/32W
MF
NOSTUFF
2
1
2
5
6
10
17
18
35
40
48
50
57
60
61
71
72
81
82
97
100
101
110
112
130
131
139
140
155
156
165
166
178
179
3
66
49
52
111
129
128
85
36
38
37
39
147
125
123
169
171
150
170
153
152
90
151
91
122
87
88
20
19
23
22
26
25
127
92
119
30
15
16
32
124
86
126
0402-0.1MM
10V
1
2
X5R-CERM
0402-0.1MM
10V
1
2
81
81
81
81
79
50
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
SM
1
5%
NP0-C0G
01005
WLAN
2
0402
CERM
4V
2
50
79
50
10%
X5R
6.3V
01005
2
5%
16V
01005
2
79
50
80
79
50
79
50
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
80
79
50
79
50
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
REF DES
BOM OPTION
PART NUMBER
ALTERNATE FOR
PART NUMBER
GND
ANT_SW_3P3
5G_ANT_CORE1
5G_ANT_CORE0
2G_ANT_CORE0
2G_ANT_CORE1
FAST_UART_CTS_IN
WL_DEV_WAKE
FAST_UART_TX
FAST_UART_RTS_OUT
VBAT_VCC
VBAT_RF_VCC
VBAT_RF_VCC
VBAT_VCC
FAST_UART_RX
BT_REG_ON
JTAG_TRST*
JTAG_SEL
JTAG_TCK
SECI_OUT
WL_REG_ON
SECI_IN
LPO_IN
GP15
CXT_B/TDO
CXT_A/TDI
PCIE_REFCLK-
PCIE_REFCLK+
SR_VLX
PCIE_PERST*
PCIE_RD-
PCIE_RD+
PCIE_TD-
PCIE_TD+
WL_HOST_WAKE
PCIE_CLKREQ*
BT_DEV_WAKE
BT_UART_TXD
BT_UART_CTS*
BT_UART_RTS*
BT_UART_RXD
CBUCK_EXT
WLAN_TIME_SYNC
LHL_GPIO2
2GHZ_C0/BT
2GHZ UAT
THE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
D
C
B
A
PAGE
BRANCH
QTY
DESCRIPTION
PART#
CRITICAL
OUTPUT
GND
LO
HI
RF4
RF1
VC
GND
RF3
VDD

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